reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
 1628     for (auto I = BitGroups.begin(); I != BitGroups.end();) {
 1631       auto IP = (I == BitGroups.begin()) ?
 1632                 std::prev(BitGroups.end()) : std::prev(I);
 1633       if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
 1633       if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
 1633       if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
 1634           I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
 1634           I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
 1637                           << I->V.getNode() << " RLAmt = " << I->RLAmt << " ["
 1637                           << I->V.getNode() << " RLAmt = " << I->RLAmt << " ["
 1638                           << I->StartIdx << ", " << I->EndIdx
 1638                           << I->StartIdx << ", " << I->EndIdx
 1642         IP->EndIdx = I->EndIdx;
 1643         IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
 1645         I = BitGroups.erase(I);
 1645         I = BitGroups.erase(I);
 1654         if (I->StartIdx == 32 && I->EndIdx == 63) {
 1654         if (I->StartIdx == 32 && I->EndIdx == 63) {
 1655           assert(std::next(I) == BitGroups.end() &&
 1659           if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
 1659           if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
 1660               (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
 1660               (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
 1661               IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
 1662               IsAllLow32(*I)) {
 1664             LLVM_DEBUG(dbgs() << "\tcombining bit group for " << I->V.getNode()
 1665                               << " RLAmt = " << I->RLAmt << " [" << I->StartIdx
 1665                               << " RLAmt = " << I->RLAmt << " [" << I->StartIdx
 1666                               << ", " << I->EndIdx
 1677               IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
 1679               I = BitGroups.erase(I);
 1679               I = BitGroups.erase(I);
 1685               IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
 1687               I = BitGroups.erase(I);
 1687               I = BitGroups.erase(I);
 1698       ++I;