reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
546 if (!MI->isInlineAsm()) { 547 for (const MachineOperand &MO: MI->operands()) { 571 switch (MI->getOpcode()) { 576 return LowerSTACKMAP(SM, *MI); 578 return LowerPATCHPOINT(SM, *MI); 627 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 681 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 686 const MachineOperand &MO = MI->getOperand(1); 739 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 744 const MachineOperand &MO = MI->getOperand(1); 768 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 773 const MachineOperand &MO = MI->getOperand(2); 798 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 803 const MachineOperand &MO = MI->getOperand(1); 826 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 834 const MachineOperand &MO = MI->getOperand(2); 866 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 874 const MachineOperand &MO = MI->getOperand(1); 899 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 906 const MachineOperand &MO = MI->getOperand(2); 924 const MachineOperand &MO = MI->getOperand(2); 931 .addReg(MI->getOperand(0).getReg()) 932 .addReg(MI->getOperand(1).getReg()) 939 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); 943 const MachineOperand &MO = MI->getOperand(1); 972 .addReg(MI->getOperand(0).getReg())); 974 .addReg(MI->getOperand(1).getReg()) 976 .addReg(MI->getOperand(0).getReg())); 978 .addReg(MI->getOperand(0).getReg()) 979 .addReg(MI->getOperand(1).getReg()) 980 .addReg(MI->getOperand(0).getReg())); 991 .addReg(MI->getOperand(0).getReg()) 994 .addReg(MI->getOperand(0).getReg()) 995 .addReg(MI->getOperand(0).getReg()) 1003 const MachineOperand &MO = MI->getOperand(2); 1010 .addReg(MI->getOperand(0).getReg()) 1011 .addReg(MI->getOperand(1).getReg()) 1021 const MachineOperand &MO = MI->getOperand(2); 1030 .addReg(MI->getOperand(0).getReg()) 1031 .addReg(MI->getOperand(1).getReg()) 1041 EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD); 1048 const MachineOperand &MO = MI->getOperand(2); 1055 .addReg(MI->getOperand(0).getReg()) 1056 .addReg(MI->getOperand(1).getReg()) 1066 const MachineOperand &MO = MI->getOperand(2); 1075 .addReg(MI->getOperand(0).getReg()) 1076 .addReg(MI->getOperand(1).getReg()) 1086 EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD); 1095 const MachineOperand &MO = MI->getOperand(2); 1104 .addReg(MI->getOperand(0).getReg()) 1105 .addReg(MI->getOperand(1).getReg()) 1115 const MachineOperand &MO = MI->getOperand(2); 1123 .addReg(MI->getOperand(0).getReg()) 1124 .addReg(MI->getOperand(1).getReg()) 1134 MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; 1136 getRegisterName(MI->getOperand(1).getReg())); 1138 .addReg(MI->getOperand(0).getReg())); 1148 MI->getOpcode() == PPC::MTOCRF ? PPC::MTCRF : PPC::MTCRF8; 1150 ->getEncodingValue(MI->getOperand(0).getReg()); 1152 getRegisterName(MI->getOperand(0).getReg())); 1155 .addReg(MI->getOperand(1).getReg())); 1170 unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; 1171 const MachineOperand &MO = MI->getOperand(OpNum); 1180 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin);