|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenGlobalISel.inc 642 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/Mips/MipsInstructionSelector.cpp 93 const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
105 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
136 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
142 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
148 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
156 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
158 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
169 const unsigned RegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
243 (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
249 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
273 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
279 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
322 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
330 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
341 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
352 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
359 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
379 *RBI.getRegBank(DestReg, MRI, TRI), RBI);
379 *RBI.getRegBank(DestReg, MRI, TRI), RBI);
382 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
434 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
441 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
464 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI),
465 RBI));
490 if (!MTC1.constrainAllUses(TII, TRI, RBI))
505 if (!PairF64.constrainAllUses(TII, TRI, RBI))
539 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
545 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
570 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
583 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
593 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
602 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
699 if (!MIB.constrainAllUses(TII, TRI, RBI))
770 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
778 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
798 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
805 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
816 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);