reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
231 MachineBasicBlock &MBB = *I.getParent(); 235 if (!isPreISelGenericOpcode(I.getOpcode())) { 236 if (I.isCopy()) 237 return selectCopy(I, MRI); 242 if (I.getOpcode() == Mips::G_MUL && 243 (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() == 245 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) 245 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) 246 .add(I.getOperand(0)) 247 .add(I.getOperand(1)) 248 .add(I.getOperand(2)); 254 I.eraseFromParent(); 258 if (selectImpl(I, *CoverageInfo)) 264 switch (I.getOpcode()) { 269 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) 269 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) 271 .add(I.getOperand(1)) 272 .add(I.getOperand(2)); 276 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) 276 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) 277 .addDef(I.getOperand(0).getReg()) 282 I.eraseFromParent(); 286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 287 .add(I.getOperand(0)) 288 .add(I.getOperand(1)) 289 .add(I.getOperand(2)); 294 I.setDesc(TII.get(COPY)); 295 return selectCopy(I, MRI); 298 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 298 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 299 .add(I.getOperand(0)) 300 .add(I.getOperand(1)) 305 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) 305 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) 306 .add(I.getOperand(0)) 308 .add(I.getOperand(1)); 318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) 318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) 320 .addUse(I.getOperand(2).getReg()) 326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 328 .addUse(I.getOperand(0).getReg()) 335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 338 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO) 347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) 357 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) 357 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) 362 I.eraseFromParent(); 366 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) 366 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) 367 .add(I.getOperand(0)); 371 const Register DestReg = I.getOperand(0).getReg(); 381 I.setDesc(TII.get(TargetOpcode::PHI)); 388 const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); 389 if (NewOpc == I.getOpcode()) 392 MachineOperand BaseAddr = I.getOperand(1); 401 MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg()); 413 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) 413 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) 414 .add(I.getOperand(0)) 417 .addMemOperand(*I.memoperands_begin()); 425 bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; 425 bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; 426 bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV; 426 bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV; 429 PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(), 429 PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(), 432 .add(I.getOperand(1)) 433 .add(I.getOperand(2)); 437 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), 437 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), 439 .addDef(I.getOperand(0).getReg()) 444 I.eraseFromParent(); 449 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) 449 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) 450 .add(I.getOperand(0)) 451 .add(I.getOperand(2)) 452 .add(I.getOperand(1)) 453 .add(I.getOperand(3)); 457 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) 457 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) 458 .add(I.getOperand(0)); 463 MRI.getType(I.getOperand(0).getReg()).getSizeInBits(), 464 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI), 469 MachineIRBuilder B(I); 470 if (!materialize32BitImm(I.getOperand(0).getReg(), 471 I.getOperand(1).getCImm()->getValue(), B)) 474 I.eraseFromParent(); 478 const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF(); 480 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); 484 MachineIRBuilder B(I); 489 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); 496 MachineIRBuilder B(I); 504 {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); 509 I.eraseFromParent(); 513 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); 517 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) 517 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) 518 .add(I.getOperand(0)) 519 .add(I.getOperand(1)); 523 unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits(); 524 unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); 536 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) 536 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) 538 .addUse(I.getOperand(1).getReg()); 542 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) 542 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) 543 .addDef(I.getOperand(0).getReg()) 548 I.eraseFromParent(); 552 const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); 554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 555 .addDef(I.getOperand(0).getReg()) 563 if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL) 578 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 578 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 579 .addDef(I.getOperand(0).getReg()) 589 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) 589 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) 597 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 597 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 598 .addDef(I.getOperand(0).getReg()) 605 I.eraseFromParent(); 610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) 611 .addDef(I.getOperand(0).getReg()) 614 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT) 620 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) 620 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) 621 .addDef(I.getOperand(0).getReg()) 622 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI); 641 Register ICMPReg = I.getOperand(0).getReg(); 643 Register LHS = I.getOperand(2).getReg(); 644 Register RHS = I.getOperand(3).getReg(); 646 static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate()); 689 MachineIRBuilder B(I); 703 I.eraseFromParent(); 710 I.getOperand(1).getPredicate())) { 757 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 757 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) 762 unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); 766 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) 766 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) 767 .addUse(I.getOperand(2).getReg()) 768 .addUse(I.getOperand(3).getReg()) 773 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) 773 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) 774 .addDef(I.getOperand(0).getReg()) 781 I.eraseFromParent(); 785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); 785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); 794 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) 794 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) 801 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) 801 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) 803 .addUse(I.getOperand(0).getReg()) 808 I.eraseFromParent(); 815 I.eraseFromParent();