reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
127 if (!Subtarget.useSoftFloat()) 423 if (Subtarget.inMips16HardFloat()) { 515 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 578 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 644 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 710 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 727 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 760 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 779 const TargetInstrInfo *TII = Subtarget.getInstrInfo();lib/Target/Mips/MipsISelLowering.cpp
115 if (Subtarget.isABI_O32()) { 128 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 310 if (Subtarget.hasMips32r6()) 363 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { 368 if (Subtarget.isGP64bit()) { 383 if (!Subtarget.isGP64bit()) { 390 if (Subtarget.isGP64bit()) 416 if (Subtarget.hasCnMips()) { 430 if (!Subtarget.hasMips32r2()) 433 if (!Subtarget.hasMips64r2()) 470 if (!Subtarget.isGP64bit()) { 475 if (!Subtarget.hasMips32r2()) { 481 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 481 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 483 if (!Subtarget.hasMips64()) 486 if (!Subtarget.hasMips32r2()) 488 if (!Subtarget.hasMips64r2()) 491 if (Subtarget.isGP64bit()) { 517 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); 528 isMicroMips = Subtarget.inMicroMipsMode(); 547 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 548 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 548 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 549 !Subtarget.inMicroMipsMode(); 554 Subtarget.useXGOT()) 1162 return performDivRemCombine(N, DAG, DCI, Subtarget); 1164 return performSELECTCombine(N, DAG, DCI, Subtarget); 1167 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1169 return performANDCombine(N, DAG, DCI, Subtarget); 1171 return performORCombine(N, DAG, DCI, Subtarget); 1173 return performADDCombine(N, DAG, DCI, Subtarget); 1175 return performSHLCombine(N, DAG, DCI, Subtarget); 1177 return performSUBCombine(N, DAG, DCI, Subtarget); 1184 return Subtarget.hasMips32(); 1188 return Subtarget.hasMips32(); 1376 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1386 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1393 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1427 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1541 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1544 if (Subtarget.hasMips32r2() && Size == 1) { 1549 if (Subtarget.hasMips32r2() && Size == 2) { 1579 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1676 if (Subtarget.isLittle()) { 1733 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1788 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1857 if (Subtarget.isLittle()) { 1908 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1908 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1928 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1928 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1940 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1940 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1969 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1988 if (Subtarget.useXGOT()) 2006 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2101 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2123 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2194 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2302 if (Subtarget.isGP64bit()) 2303 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2305 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2368 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); 2370 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); 2455 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2488 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2517 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2517 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2519 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2556 if (Subtarget.systemSupportsUnalignedAccess()) 2564 bool IsLittle = Subtarget.isLittle(); 2683 if (!Subtarget.systemSupportsUnalignedAccess() && 2686 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2688 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2704 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2946 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2950 if (Subtarget.inMips16HardFloat()) { 2983 Subtarget.inMips16Mode() || 3031 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3039 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 3145 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3166 if (!Subtarget.isLittle()) 3238 if (!Subtarget.isABICalls() && !IsPIC) { 3243 if (Subtarget.useLongCalls()) 3244 Callee = Subtarget.hasSym32() 3248 bool UseLongCalls = Subtarget.useLongCalls(); 3258 Callee = Subtarget.hasSym32() 3271 else if (Subtarget.useXGOT()) { 3293 else if (Subtarget.useXGOT()) { 3545 if (!Subtarget.isLittle()) 3560 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3815 if (Subtarget.hasMSA() && type->isVectorTy() && 3870 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 3878 Subtarget.getRegisterInfo(); 3928 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3962 if (Subtarget.inMips16Mode()) 3966 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3968 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3983 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3984 if (Subtarget.isFP64bit()) 4145 if (Subtarget.hasMips64()) 4170 return Subtarget.useSoftFloat(); 4181 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4235 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4328 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4371 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4381 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4418 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4418 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4423 Subtarget.getInstrInfo(); 4494 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4494 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4498 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4573 if (Subtarget.isGP64bit()) {lib/Target/Mips/MipsSEISelLowering.cpp
69 if (Subtarget.isGP64bit()) 72 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { 72 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { 84 if (Subtarget.hasDSP()) { 107 if (Subtarget.hasMips32r2()) { 113 if (Subtarget.hasDSPR2()) 116 if (Subtarget.hasMSA()) { 170 if (!Subtarget.useSoftFloat()) { 174 if (!Subtarget.isSingleFloat()) { 175 if (Subtarget.isFP64bit()) 187 if (Subtarget.hasCnMips()) 189 else if (Subtarget.isGP64bit()) 192 if (Subtarget.isGP64bit()) { 216 if (Subtarget.hasMips32r2() && !Subtarget.useSoftFloat() && 216 if (Subtarget.hasMips32r2() && !Subtarget.useSoftFloat() && 217 !Subtarget.hasMips64()) { 226 if (Subtarget.hasMips32r6()) { 254 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6"); 273 if (Subtarget.hasMips64r6()) { 298 computeRegisterProperties(Subtarget.getRegisterInfo()); 310 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; 409 if(!Subtarget.hasMips32r6()) 427 if (Subtarget.systemSupportsUnalignedAccess()) { 1031 Val = performANDCombine(N, DAG, DCI, Subtarget); 1034 Val = performORCombine(N, DAG, DCI, Subtarget); 1037 return performMULCombine(N, DAG, DCI, this, Subtarget); 1039 Val = performSHLCombine(N, DAG, DCI, Subtarget); 1042 return performSRACombine(N, DAG, DCI, Subtarget); 1044 return performSRLCombine(N, DAG, DCI, Subtarget); 1048 Val = performXORCombine(N, DAG, Subtarget); 1194 if (!Subtarget.isLittle()) 1217 if (!Subtarget.isLittle()) 1266 assert(!Subtarget.hasMips32r6()); 1667 !Subtarget.isLittle()); 1703 !Subtarget.isLittle()); 1778 if (Subtarget.hasMips64()) 1793 if (Subtarget.hasMips64()) 2363 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget); 2398 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget); 2468 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) 2473 !Subtarget.isLittle()) && SplatBitSize <= 64) { 3037 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3106 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3171 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3180 if (!Subtarget.useOddSPReg()) { 3191 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass 3215 assert(Subtarget.isFP64bit()); 3217 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3246 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3254 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass 3280 assert(Subtarget.isFP64bit()); 3282 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3328 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3339 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 3340 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; 3341 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; 3419 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB), 3421 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO) 3442 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3448 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass 3451 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass 3475 assert(Subtarget.isFP64bit()); 3477 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3511 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3524 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass 3566 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3576 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass 3656 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); 3656 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); 3658 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; 3659 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64; 3661 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3761 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); 3761 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); 3763 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; 3764 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64; 3766 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3819 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3848 const TargetInstrInfo *TII = Subtarget.getInstrInfo();