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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
lib/Target/Mips/MipsFastISel.cpp 229 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
References
gen/lib/Target/Mips/MipsGenFastISel.inc 1231 return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1234 return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1237 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1240 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1249 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1258 return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1267 return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1276 return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1285 return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1294 return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1303 return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1328 return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1331 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1340 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1359 return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1377 return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1380 return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1383 return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1386 return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1395 return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1404 return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1413 return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1422 return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1431 return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1454 return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1457 return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1466 return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1469 return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1472 return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1475 return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1484 return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1493 return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1514 return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1517 return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1526 return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1529 return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1532 return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1535 return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1544 return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1553 return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1574 return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1577 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1586 return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1589 return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1592 return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1595 return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1604 return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1613 return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1634 return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1637 return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1646 return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1649 return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1652 return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1655 return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1664 return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1673 return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1694 return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1697 return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1700 return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1703 return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1706 return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1715 return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1718 return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1727 return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1736 return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1745 return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1754 return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1763 return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1787 return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1790 return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1799 return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1818 return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1821 return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1830 return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1849 return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1852 return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1855 return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1858 return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1867 return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1876 return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1885 return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1894 return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1903 return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1926 return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1929 return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1947 return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1950 return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1959 return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1968 return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1977 return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1986 return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1995 return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2018 return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2021 return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2024 return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2033 return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2042 return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2051 return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2060 return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2082 return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2091 return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2100 return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2109 return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2130 return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2139 return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2148 return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2157 return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2178 return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2181 return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2184 return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2193 return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2202 return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2211 return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2220 return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2242 return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2245 return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2254 return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2263 return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2272 return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2281 return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2290 return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2313 return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2316 return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2319 return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2328 return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2337 return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2346 return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2355 return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2377 return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2380 return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2383 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2386 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2395 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2404 return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2413 return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2422 return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2431 return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2440 return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2449 return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2474 return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2477 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2480 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2489 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2508 return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2511 return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2520 return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2529 return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2538 return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2547 return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2556 return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2579 return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2588 return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2597 return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2606 return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2627 return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2636 return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2645 return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2654 return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2675 return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2678 return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2687 return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2696 return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2705 return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2714 return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2723 return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2746 return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2749 return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2752 return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2755 return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2764 return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2773 return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2782 return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2791 return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2800 return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2823 return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2826 return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2844 return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2847 return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2856 return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2875 return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2893 return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2896 return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2905 return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2924 return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2941 return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2947 return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2964 return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2973 return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2982 return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2991 return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3012 return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3021 return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3030 return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3039 return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3060 return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3069 return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3078 return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3087 return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3108 return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3117 return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3126 return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3135 return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3156 return fastEmitInst_rr(Mips::PseudoMTLOHI_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3159 return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3162 return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3171 return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3190 return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3193 return fastEmitInst_rr(Mips::PseudoMULT_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3196 return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3199 return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3208 return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3227 return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3230 return fastEmitInst_rr(Mips::PseudoMULTu_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3233 return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3236 return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3245 return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3264 return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3273 return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3282 return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3291 return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3312 return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3321 return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3330 return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3339 return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3360 return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3369 return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3378 return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3387 return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);