reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
137 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); 287 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc()); 301 if (HII->isDeallocRet(MI)) 357 if (HII->isHVXVec(MI) && MI.mayStore()) 359 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; 359 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; 362 return HII->mayBeNewStore(MI); 372 int CurOpcode = HII->getDotCurOp(MI); 373 MI.setDesc(HII->get(CurOpcode)); 381 if (HII->isDotCurInst(*BI)) { 394 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI))); 394 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI))); 402 if (!HII->isHVXVec(MI)) 404 if (!HII->isHVXVec(*MII)) 408 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI)) 408 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI)) 411 if (!HII->mayBeCurLoad(MI)) 456 NewOpcode = HII->getDotNewPredOp(MI, MBPI); 458 NewOpcode = HII->getDotNewOp(MI); 459 MI.setDesc(HII->get(NewOpcode)); 464 int NewOpcode = HII->getDotOldOp(MI); 465 MI.setDesc(HII->get(NewOpcode)); 483 if (HII->isValidOffset(Opc, NewOff, HRI)) { 514 if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI)) 517 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ)) 530 if (!HII->getIncrementValue(MJ, Incr)) 534 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) 546 if (!HII->getBaseAndOffsetPosition(MI, BP, OP)) 646 if (!HII->mayBeNewStore(MI)) 657 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF); 672 if (HII->isPostIncrement(MI) && 673 getPostIncrementOperand(MI, HII).getReg() == DepReg) { 677 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() && 678 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) { 692 if (HII->isPredicated(PacketMI)) { 693 if (!HII->isPredicated(MI)) 735 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) || 735 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) || 736 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII)) 736 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII)) 775 if (!HII->isPostIncrement(MI)) { 815 if (!HII->mayBeNewStore(MI)) 846 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI)) 846 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI)) 870 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); 876 return HII->predCanBeUsedAsDotNew(PI, DepReg); 878 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI)) 883 int NewOpcode = HII->getDotNewOp(MI); 884 const MCInstrDesc &D = HII->get(NewOpcode); 917 if (!HII->isPredicated(*I)) 962 if (getPredicateSense(MI1, HII) == PK_Unknown || 963 getPredicateSense(MI2, HII) == PK_Unknown) 1015 unsigned PReg1 = getPredicatedRegister(MI1, HII); 1016 unsigned PReg2 = getPredicatedRegister(MI2, HII); 1020 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && 1020 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && 1021 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); 1021 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); 1077 if (HII->isSolo(MI)) 1145 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII); 1145 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII); 1199 if (HII->isPredicated(I) || HII->isPredicated(J)) 1199 if (HII->isPredicated(I) || HII->isPredicated(J)) 1223 if ((HII->isSaveCalleeSavedRegsCall(I) && 1225 (HII->isSaveCalleeSavedRegsCall(J) && 1237 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI)) 1237 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI)) 1239 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) 1239 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) 1239 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) 1244 if (HII->isLoopN(I) && isBadForLoopN(J)) 1246 if (HII->isLoopN(J) && isBadForLoopN(I)) 1251 return HII->isDeallocRet(I) && 1271 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call"); 1293 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I)) 1293 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I)) 1293 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I)) 1298 bool MopStI = HII->isMemOp(I) || StoreI; 1299 bool MopStJ = HII->isMemOp(J) || StoreJ; 1304 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J)); 1304 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J)); 1349 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) { 1374 HII->isLoopN(*PI)) { 1425 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) { 1425 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) { 1439 if (DepType == SDep::Data && HII->isDotCurInst(J)) { 1440 if (HII->isHVXVec(I)) 1454 if (HII->isNewValueJump(I)) 1460 if (HII->isPredicated(I) && HII->isPredicated(J) && 1460 if (HII->isPredicated(I) && HII->isPredicated(J) && 1517 bool NVStoreJ = HII->isNewValueStore(J); 1518 bool NVStoreI = HII->isNewValueStore(I); 1519 bool IsVecJ = HII->isHVXVec(J); 1520 bool IsVecI = HII->isHVXVec(I); 1529 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI)) 1529 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI)) 1676 if (HII->isMemOp(*MJ)) 1680 if (MJ->mayStore() && !HII->isNewValueStore(*MJ)) 1704 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI); 1704 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI); 1717 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI); 1717 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI); 1788 for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI)) 1799 HII->setBundleNoShuf(BundleMII); 1863 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I)) 1863 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))