reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
 1319   MachineBasicBlock::iterator II = I.getIterator();
 1322   assert(!isSoloInstruction(I) && "Unexpected solo instr!");
 1324   if (cannotCoexist(I, J))
 1327   Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
 1327   Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
 1335   Dependence = hasRegMaskDependence(I, J);
 1342   Dependence = hasDualStoreDependence(I, J);
 1347   MachineBasicBlock::iterator NextMII = I.getIterator();
 1349   if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
 1356     if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
 1425     if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
 1425     if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
 1425     if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
 1425     if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
 1428       if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
 1440       if (HII->isHVXVec(I))
 1446       if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
 1447         if (promoteToDotNew(I, DepType, II, RC)) {
 1449           if (cannotCoexist(I, J))
 1454       if (HII->isNewValueJump(I))
 1460     if (HII->isPredicated(I) && HII->isPredicated(J) &&
 1461         arePredicatesComplements(I, J)) {
 1479       IgnoreDepMIs.push_back(&I);
 1485     if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
 1491     if (I.isConditionalBranch() && DepType != SDep::Data &&
 1508         bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
 1516       bool LoadI = I.mayLoad(), StoreI = I.mayStore();
 1516       bool LoadI = I.mayLoad(), StoreI = I.mayStore();
 1518       bool NVStoreI = HII->isNewValueStore(I);
 1520       bool IsVecI = HII->isHVXVec(I);
 1526            I.getOpcode() != Hexagon::S2_allocframe) &&
 1528            I.getOpcode() != Hexagon::L2_deallocframe) &&
 1529           (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
 1532         if (StoreJ && LoadI && alias(J, I)) {
 1556       unsigned Opc = I.getOpcode();
 1562           if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
 1567             GlueAllocframeStore = useCallersSP(I);
 1587       for (const MachineOperand &Op : I.operands()) {