reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
200 auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo(); 201 auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); 205 for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) { 207 if (DAG->SUnits[su].getInstr()->isCall()) 208 LastSequentialCall = &DAG->SUnits[su]; 210 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) 211 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); 211 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); 214 shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1])) 214 shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1])) 215 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); 215 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); 215 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); 231 const MachineInstr *MI = DAG->SUnits[su].getInstr(); 245 LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su]; 250 LastVRegUse[*AI] != &DAG->SUnits[su]) 252 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier)); 252 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));