reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
135 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) { 136 assert(MI.getNumOperands() == 2); 137 MachineOperand &Dst = MI.getOperand(0); 138 MachineOperand &Src = MI.getOperand(1); 153 if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) { 154 assert(MI.getNumOperands() == 3); 155 MachineOperand &Dst = MI.getOperand(0); 156 MachineOperand &Src1 = MI.getOperand(1); 157 MachineOperand &Src2 = MI.getOperand(2); 170 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) { 171 assert(MI.getNumOperands() == 3); 172 MachineOperand &Dst = MI.getOperand(0); 173 MachineOperand &Src1 = MI.getOperand(1); 174 MachineOperand &Src2 = MI.getOperand(2); 184 if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) { 185 assert(MI.getNumOperands() == 2); 186 MachineOperand &Dst = MI.getOperand(0); 187 MachineOperand &Src = MI.getOperand(1); 202 if (!DisableOptSZExt && MI.isCopy()) { 203 assert(MI.getNumOperands() == 2); 204 MachineOperand &Dst = MI.getOperand(0); 205 MachineOperand &Src = MI.getOperand(1); 218 MI.RemoveOperand(1); 219 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 225 MI.RemoveOperand(1); 226 MI.addOperand(MachineOperand::CreateReg( 238 if (QII->isPredicated(MI)) { 239 MachineOperand &Op0 = MI.getOperand(0); 249 MI.getOperand(0).setReg(PeepholeSrc); 251 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode()); 252 MI.setDesc(QII->get(NewOp)); 261 unsigned Op = MI.getOpcode(); 278 Register PSrc = MI.getOperand(PR).getReg(); 280 BuildMI(*MBB, MI.getIterator(), MI.getDebugLoc(), 280 BuildMI(*MBB, MI.getIterator(), MI.getDebugLoc(), 281 QII->get(NewOp), MI.getOperand(0).getReg()) 283 .add(MI.getOperand(S2)) 284 .add(MI.getOperand(S1)); 286 MI.eraseFromParent();