reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
93 dbgs() << printReg(Reg, TRI, SubReg); 97 return (Reg == R.Reg) && (SubReg == R.SubReg); 97 return (Reg == R.Reg) && (SubReg == R.SubReg); 626 assert(Register::isVirtualRegister(DefR.Reg)); 633 const LatticeCell &T = Cells.get(DefR.Reg); 635 Cells.update(DefR.Reg, Bottom); 637 visitUsesOf(DefR.Reg); 641 LatticeCell DefC = Cells.get(DefR.Reg); 655 if (!Register::isVirtualRegister(UseR.Reg)) 658 if (!Cells.has(UseR.Reg)) 662 bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); 664 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC 668 Cells.update(DefR.Reg, DefC); 673 visitUsesOf(DefR.Reg); 697 if (!Register::isVirtualRegister(DefR.Reg)) 702 const LatticeCell &T = Cells.get(DefR.Reg); 704 Cells.update(DefR.Reg, Bottom); 708 if (!Outputs.has(DefR.Reg)) 710 LatticeCell RC = Cells.get(DefR.Reg); 711 Changed = RC.meet(Outputs.get(DefR.Reg)); 712 Cells.update(DefR.Reg, RC); 715 visitUsesOf(DefR.Reg); 1073 if (!Register::isVirtualRegister(R.Reg)) 1075 const LatticeCell &L = Inputs.get(R.Reg); 1099 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1099 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1138 assert(Inputs.has(R1.Reg)); 1165 assert(Inputs.has(R1.Reg)); 1363 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1363 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1364 const LatticeCell &L1 = Inputs.get(R2.Reg); 1365 const LatticeCell &L2 = Inputs.get(R2.Reg); 1394 assert(Inputs.has(R1.Reg)); 1430 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1430 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1431 const LatticeCell &L1 = Inputs.get(R2.Reg); 1432 const LatticeCell &L2 = Inputs.get(R2.Reg); 1461 assert(Inputs.has(R1.Reg)); 1497 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1497 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 1526 assert(Inputs.has(R1.Reg)); 1559 assert(Inputs.has(R1.Reg)); 1590 assert(Inputs.has(R1.Reg)); 1655 assert(Inputs.has(R1.Reg)); 1690 assert(Inputs.has(R1.Reg)); 1726 assert(Inputs.has(R1.Reg)); 1784 assert(Inputs.has(R1.Reg)); 1929 if (!Register::isVirtualRegister(DefR.Reg)) 1938 Outputs.update(DefR.Reg, RC); 1944 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); 1960 Outputs.update(DefR.Reg, RC); 1983 unsigned W = getRegBitWidth(DefR.Reg); 1989 LatticeCell RC = Outputs.get(DefR.Reg); 1991 Outputs.update(DefR.Reg, RC); 1998 LatticeCell RC = Outputs.get(DefR.Reg); 2003 Outputs.update(DefR.Reg, RC); 2032 LatticeCell RC = Outputs.get(DefR.Reg); 2034 Outputs.update(DefR.Reg, RC); 2044 LatticeCell RC = Outputs.get(DefR.Reg); 2048 Outputs.update(DefR.Reg, RC); 2084 assert(Inputs.has(R1.Reg)); 2093 LatticeCell RC = Outputs.get(DefR.Reg); 2100 Outputs.update(DefR.Reg, RC); 2116 assert(Inputs.has(R1.Reg)); 2125 LatticeCell RC = Outputs.get(DefR.Reg); 2132 Outputs.update(DefR.Reg, RC); 2144 unsigned BW = getRegBitWidth(R1.Reg); 2147 LatticeCell RC = Outputs.get(DefR.Reg); 2163 Outputs.update(DefR.Reg, RC); 2200 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); 2290 assert(Inputs.has(PR.Reg)); 2291 const LatticeCell &PredC = Inputs.get(PR.Reg); 2509 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); 2509 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); 2577 LatticeCell L = Outputs.get(DefR.Reg); 2581 Outputs.update(DefR.Reg, L); 2661 Outputs.update(DefR.Reg, RC); 2670 assert(Inputs.has(CR.Reg)); 2685 LatticeCell RC = Outputs.get(DefR.Reg); 2689 unsigned W = getRegBitWidth(DefR.Reg); 2693 Outputs.update(DefR.Reg, RC); 2698 const LatticeCell &LR = Inputs.get(R.Reg); 2703 Outputs.update(DefR.Reg, RC); 2713 assert(Inputs.has(R1.Reg)); 2743 unsigned BW = getRegBitWidth(DefR.Reg); 2744 LatticeCell RC = Outputs.get(DefR.Reg); 2749 Outputs.update(DefR.Reg, RC); 2758 assert(Inputs.has(R1.Reg)); 2759 LatticeCell RC = Outputs.get(DefR.Reg); 2778 Outputs.update(DefR.Reg, RC); 2796 if (!Register::isVirtualRegister(R.Reg)) 2800 if (!MI.isPHI() && !Inputs.has(R.Reg)) { 2801 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg) 2805 const LatticeCell &L = Inputs.get(R.Reg); 2965 assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg)); 2965 assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg)); 2979 unsigned NewR = R1.Reg; 2982 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); 2985 .addReg(R1.Reg, getRegState(Acc), R1.SubReg); 2987 replaceAllRegUsesWith(DefR.Reg, NewR); 3011 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); 3018 replaceAllRegUsesWith(DefR.Reg, NewR); 3027 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 3027 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 3046 unsigned NewR = SR.Reg; 3048 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); 3051 .addReg(SR.Reg, getRegState(SO), SR.SubReg); 3053 replaceAllRegUsesWith(DefR.Reg, NewR); 3063 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 3063 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); 3078 unsigned NewR = SR.Reg; 3080 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); 3083 .addReg(SR.Reg, getRegState(SO), SR.SubReg); 3085 replaceAllRegUsesWith(DefR.Reg, NewR);