reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/Hexagon/HexagonConstExtenders.cpp
  300         return Rs.Reg == 0;
  303         return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
  303         return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
  309         if (Rs != Ex.Rs)
  309         if (Rs != Ex.Rs)
  310           return Rs < Ex.Rs;
  310           return Rs < Ex.Rs;
  468     if (P.Ex.Rs.Reg != 0)
  469       OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
  469       OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
 1170           ED.Expr.Rs = MI.getOperand(OpNum-1);
 1173         ED.Expr.Rs = MI.getOperand(OpNum-2);
 1196         ED.Expr.Rs = MI.getOperand(OpNum-1);
 1201         ED.Expr.Rs = MI.getOperand(OpNum-1);
 1205         ED.Expr.Rs = MI.getOperand(OpNum+1);
 1209         ED.Expr.Rs = MI.getOperand(OpNum+1);
 1460                       return Extenders[I].Expr.Rs.isSlot();
 1464       return ED.Expr.Rs.isSlot() == IsStack &&
 1503   Register Rs = ExtI.second.Rs;  // Only one reg allowed now.
 1538   if (Ex.Rs.isSlot()) {
 1543               .add(MachineOperand(Ex.Rs))
 1546     assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");
 1546     assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");
 1556                   .add(MachineOperand(Ex.Rs));
 1560                   .add(MachineOperand(Ex.Rs))
 1569                 .add(MachineOperand(Ex.Rs))
 1761     assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
 1784     assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch");