reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
236 Reg = Op.getReg(); 239 Reg = llvm::Register::index2StackSlot(Op.getIndex()); 244 return Reg != 0 && !llvm::Register::isStackSlot(Reg) && 244 return Reg != 0 && !llvm::Register::isStackSlot(Reg) && 245 llvm::Register::isVirtualRegister(Reg); 248 return Reg != 0 && llvm::Register::isStackSlot(Reg); 248 return Reg != 0 && llvm::Register::isStackSlot(Reg); 252 return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false, 255 if (llvm::Register::isStackSlot(Reg)) { 256 int FI = llvm::Register::stackSlot2Index(Reg); 261 bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; } 261 bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; } 265 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); 265 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); 265 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); 265 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); 300 return Rs.Reg == 0; 451 if (P.Rs.Reg != 0) 452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); 468 if (P.Ex.Rs.Reg != 0) 469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); 497 if (ED.Rd.Reg != 0) 498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); 1129 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) { 1278 assert(ED.Rd.Reg != 0); 1504 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr; 1546 assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register"); 1832 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); 1858 for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) { 1886 MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg); 1886 MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg); 1906 NewRegs.push_back(DefR.Reg);