reference, declarationdefinition
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reference to multiple definitions → definitions
unreferenced

References

lib/Target/ARM/ARMBaseInstrInfo.cpp
  537     return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
 2735   case ARMCC::EQ: return ARMCC::EQ;
 2735   case ARMCC::EQ: return ARMCC::EQ;
 3080         CC = ARMCC::EQ;
 3129         case ARMCC::EQ: // Z
lib/Target/ARM/ARMConstantIslandPass.cpp
 1874     if (Pred == ARMCC::EQ)
lib/Target/ARM/ARMExpandPseudoInsts.cpp
 1098       .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
lib/Target/ARM/ARMFastISel.cpp
 1200       return ARMCC::EQ;
 1285         CCMode = ARMCC::EQ;
 1323     CCMode = ARMCC::EQ;
 1684         .addImm(ARMCC::EQ)
lib/Target/ARM/ARMISelDAGToDAG.cpp
 3376         case ARMCC::EQ:
 3453         case ARMCC::EQ:
lib/Target/ARM/ARMISelLowering.cpp
 1801   case ISD::SETEQ:  return ARMCC::EQ;
 1820   case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
 1830   case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
 4311   case ARMCC::EQ:
 4402     ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
 4413     ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
 4655     CondCode = ARMCC::EQ;
 5034         CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
 6221     case ISD::SETEQ:  Opc = ARMCC::EQ; break;
 6269     case ISD::SETEQ:  Opc = ARMCC::EQ; break;
 6281     if (ST->hasNEON() && Opc == ARMCC::EQ) {
10354       .addImm(ARMCC::EQ)
10558         .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10568         .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10577       .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
12246   case ARMCC::EQ:
13976   if (CC == ARMCC::EQ) {
14284   } else if (CC == ARMCC::EQ && TrueVal == RHS) {
14311     if (CC == ARMCC::EQ && isOneConstant(TrueVal)) {
14352     if (CC == ARMCC::EQ && !isNullConstant(RHS) &&
lib/Target/ARM/ARMInstructionSelector.cpp
  398     Preds = {ARMCC::EQ, ARMCC::VS};
  402     Preds.first = ARMCC::EQ;
  795                    .add(predOps(ARMCC::EQ, ARM::CPSR));
lib/Target/ARM/ARMLowOverheadLoops.cpp
  375   MIB.addImm(ARMCC::EQ);        // condition code
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 2296     return CC == ARMCC::EQ || CC == ARMCC::NE;
 2318     return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 6165   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
 6208     Code = ARMCC::EQ;
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
 1970   case ARMCC::EQ:
lib/Target/ARM/Utils/ARMBaseInfo.h
   51   case EQ: return NE;
   52   case NE: return EQ;
   95   case ARMCC::EQ:  return "eq";
  116     .Case("eq", ARMCC::EQ)