reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
93 unsigned Opcode = MI->getOpcode(); 99 const MCOperand &Dst = MI->getOperand(0); 100 const MCOperand &MO1 = MI->getOperand(1); 101 const MCOperand &MO2 = MI->getOperand(2); 102 const MCOperand &MO3 = MI->getOperand(3); 105 printSBitModifierOperand(MI, 6, STI, O); 106 printPredicateOperand(MI, 4, STI, O); 122 const MCOperand &Dst = MI->getOperand(0); 123 const MCOperand &MO1 = MI->getOperand(1); 124 const MCOperand &MO2 = MI->getOperand(2); 127 printSBitModifierOperand(MI, 5, STI, O); 128 printPredicateOperand(MI, 3, STI, O); 149 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 149 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 152 printPredicateOperand(MI, 2, STI, O); 156 printRegisterList(MI, 4, STI, O); 163 if (MI->getOperand(2).getReg() == ARM::SP && 164 MI->getOperand(3).getImm() == -4) { 166 printPredicateOperand(MI, 4, STI, O); 168 printRegName(O, MI->getOperand(1).getReg()); 178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 181 printPredicateOperand(MI, 2, STI, O); 185 printRegisterList(MI, 4, STI, O); 192 if (MI->getOperand(2).getReg() == ARM::SP && 193 MI->getOperand(4).getImm() == 4) { 195 printPredicateOperand(MI, 5, STI, O); 197 printRegName(O, MI->getOperand(0).getReg()); 207 if (MI->getOperand(0).getReg() == ARM::SP) { 209 printPredicateOperand(MI, 2, STI, O); 211 printRegisterList(MI, 4, STI, O); 220 if (MI->getOperand(0).getReg() == ARM::SP) { 222 printPredicateOperand(MI, 2, STI, O); 224 printRegisterList(MI, 4, STI, O); 232 unsigned BaseReg = MI->getOperand(0).getReg(); 233 for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 234 if (MI->getOperand(i).getReg() == BaseReg) 240 printPredicateOperand(MI, 1, STI, O); 246 printRegisterList(MI, 3, STI, O); 263 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); 270 NewMI.addOperand(MI->getOperand(0)); 276 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i) 277 NewMI.addOperand(MI->getOperand(i)); 288 switch (MI->getOperand(0).getImm()) { 290 if (!printAliasInstr(MI, STI, O)) 291 printInstruction(MI, STI, O); 304 if (!printAliasInstr(MI, STI, O)) 305 printInstruction(MI, STI, O);