reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
767 switch (MI.getOpcode()) { 790 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 808 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 809 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 824 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 825 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 827 MCInst::iterator CCI = MI.begin(); 829 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 832 if (ARMInsts[MI.getOpcode()].isPredicable()) { 833 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 836 MI.insert(CCI, MCOperand::createReg(0)); 838 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 843 MCInst::iterator VCCI = MI.begin(); 846 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 849 if (isVectorPredicable(MI.getOpcode())) { 850 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 853 MI.insert(VCCI, MCOperand::createReg(0)); 855 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 857 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 861 MI.insert(VCCI, MI.getOperand(TiedOp)); 861 MI.insert(VCCI, MI.getOperand(TiedOp));