reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
60 virtual unsigned getReg() const = 0;
9076 switch (Operand.getReg()) {
lib/Target/ARM/AsmParser/ARMAsmParser.cpp2405 Inst.addOperand(MCOperand::createReg(getReg())); 2410 Inst.addOperand(MCOperand::createReg(getReg())); 3727 OS << "<ccout " << RegName(getReg()) << ">"; 3802 OS << "<register " << RegName(getReg()) << ">"; 3977 int SrcReg = PrevOp->getReg(); 5559 ((ARMOperand &)*Operands[4]).getReg() == 5560 ((ARMOperand &)*Operands[3]).getReg()) 6426 auto Op3Reg = Op3.getReg(); 6427 auto Op4Reg = Op4.getReg(); 6438 (Op5.isReg() && Op5.getReg() == ARM::PC); 6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) && 6466 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && 6513 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6521 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6531 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 6532 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6550 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 6551 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 6556 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 6569 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6577 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6578 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 6580 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 6581 static_cast<ARMOperand &>(*Operands[5]).getReg() && 6582 static_cast<ARMOperand &>(*Operands[3]).getReg() != 6583 static_cast<ARMOperand &>(*Operands[4]).getReg()))) 6589 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6595 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6596 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6608 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 6609 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6633 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 6635 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) 6726 if (!GPR.contains(Op2.getReg())) 6729 unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg()); 6735 if (Op2.getReg() == ARM::PC) 7104 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 7105 MRC.contains(Op2.getReg())) { 7106 unsigned Reg1 = Op1.getReg(); 7107 unsigned Reg2 = Op2.getReg(); 7135 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && 7137 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && 7649 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 7650 ((ARMOperand &)*Operands[5]).getReg()) && 7651 (((ARMOperand &)*Operands[3]).getReg() != 7652 ((ARMOperand &)*Operands[4]).getReg())) { 11841 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) 11846 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))