reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
7299 SMLoc Loc = Operands[0]->getStartLoc(); 7313 for (unsigned I = 1; I < Operands.size(); ++I) 7314 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) 7315 CondLoc = Operands[I]->getStartLoc(); 7360 for (unsigned I = 1; I < Operands.size(); ++I) 7361 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) 7362 PredLoc = Operands[I]->getStartLoc(); 7391 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, 7397 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, 7402 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, 7408 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, 7416 return Error(Operands[2]->getStartLoc(), 7421 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, 7427 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, 7433 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, 7458 return Error(Operands[3]->getStartLoc(), 7491 return Error(Operands[3]->getStartLoc(), 7535 return Error(Operands[3]->getStartLoc(), 7551 return Error(Operands[5]->getStartLoc(), 7565 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 7566 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 7569 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 7573 return Error(Operands[2]->getStartLoc(), 7578 return Error(Operands[3]->getStartLoc(), 7582 if (validatetLDMRegList(Inst, Operands, 3)) 7595 return Error(Operands.back()->getStartLoc(), 7600 if (validatetLDMRegList(Inst, Operands, 3)) 7605 if (validatetSTMRegList(Inst, Operands, 3)) 7613 return Error(Operands.back()->getStartLoc(), 7617 if (validatetLDMRegList(Inst, Operands, 3)) 7620 if (validatetSTMRegList(Inst, Operands, 3)) 7630 return Error(Operands[4]->getStartLoc(), 7638 return Error(Operands[2]->getStartLoc(), 7649 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 7649 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 7650 ((ARMOperand &)*Operands[5]).getReg()) && 7651 (((ARMOperand &)*Operands[3]).getReg() != 7652 ((ARMOperand &)*Operands[4]).getReg())) { 7653 return Error(Operands[3]->getStartLoc(), 7665 return Error(Operands[2]->getStartLoc(), 7667 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) 7675 return Error(Operands[2]->getStartLoc(), 7677 if (validatetSTMRegList(Inst, Operands, 2)) 7686 return Error(Operands[4]->getStartLoc(), 7692 return Error(Operands[4]->getStartLoc(), 7696 if (validatetSTMRegList(Inst, Operands, 4)) 7705 return Error(Operands[4]->getStartLoc(), 7720 return Error(Operands[4]->getStartLoc(), 7726 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) 7727 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7730 int op = (Operands[2]->isImm()) ? 2 : 3; 7731 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) 7732 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 7737 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) 7738 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7741 int Op = (Operands[2]->isImm()) ? 2 : 3; 7742 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) 7743 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 7748 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) 7749 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7763 int i = (Operands[3]->isImm()) ? 3 : 4; 7764 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); 7784 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " 7788 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " 7797 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || 7799 return Error(Operands[2]->getStartLoc(), 7803 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) 7804 return Error(Operands[3]->getStartLoc(), 7807 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) 7808 return Error(Operands[3]->getStartLoc(), 7814 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || 7816 return Error(Operands[1]->getStartLoc(), 7819 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) 7820 return Error(Operands[2]->getStartLoc(), 7831 Operands[3]->getStartLoc(), 7841 return Error(Operands[2]->getStartLoc(), 7859 return Error(Operands[1]->getStartLoc(), 7863 return Error(Operands[1]->getStartLoc(), 7873 return Error(Operands[5]->getStartLoc(), 7882 return Error(Operands[3]->getStartLoc(), 7888 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); 7891 return Error(Operands[3]->getStartLoc(), 7902 if (Operands[3]->getReg() == Operands[4]->getReg()) { 7902 if (Operands[3]->getReg() == Operands[4]->getReg()) { 7903 return Error (Operands[3]->getStartLoc(), 7906 if (Operands[3]->getReg() == Operands[5]->getReg()) { 7906 if (Operands[3]->getReg() == Operands[5]->getReg()) { 7907 return Error (Operands[3]->getStartLoc(), 7913 if (Operands[4]->getReg() != Operands[6]->getReg()) 7913 if (Operands[4]->getReg() != Operands[6]->getReg()) 7914 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); 7915 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != 7916 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) 7917 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); 7921 if (Operands[2]->getReg() != Operands[4]->getReg()) 7921 if (Operands[2]->getReg() != Operands[4]->getReg()) 7922 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); 7923 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != 7924 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) 7925 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");