reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6510 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 6511 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && 6512 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && 6513 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6518 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 6519 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6520 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6521 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6529 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6529 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6530 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6531 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 6532 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6533 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || 6534 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) 6542 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6542 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6543 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6544 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 6550 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 6551 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 6552 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) 6556 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 6557 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) 6568 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 6569 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6570 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6571 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6572 static_cast<ARMOperand &>(*Operands[5]).isReg() && 6577 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6578 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 6580 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 6581 static_cast<ARMOperand &>(*Operands[5]).getReg() && 6582 static_cast<ARMOperand &>(*Operands[3]).getReg() != 6583 static_cast<ARMOperand &>(*Operands[4]).getReg()))) 6588 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 6589 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6590 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6591 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6595 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6596 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6606 (Operands.size() == 5 || Operands.size() == 6) && 6606 (Operands.size() == 5 || Operands.size() == 6) && 6607 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6608 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 6609 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6610 (static_cast<ARMOperand &>(*Operands[4]).isImm() || 6611 (Operands.size() == 6 && 6612 static_cast<ARMOperand &>(*Operands[5]).isImm())))