reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
8203 switch (Inst.getOpcode()) { 8218 switch(Inst.getOpcode()) { 8236 TmpInst.addOperand(Inst.getOperand(0)); 8237 TmpInst.addOperand(Inst.getOperand(1)); 8240 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff); 8243 TmpInst.addOperand(Inst.getOperand(3)); 8244 TmpInst.addOperand(Inst.getOperand(4)); 8245 Inst = TmpInst; 8252 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 8256 TmpInst.addOperand(Inst.getOperand(0)); 8257 TmpInst.addOperand(Inst.getOperand(1)); 8258 TmpInst.addOperand(Inst.getOperand(1)); 8261 TmpInst.addOperand(Inst.getOperand(2)); 8262 TmpInst.addOperand(Inst.getOperand(3)); 8263 Inst = TmpInst; 8270 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 8274 TmpInst.addOperand(Inst.getOperand(1)); 8275 TmpInst.addOperand(Inst.getOperand(0)); 8276 TmpInst.addOperand(Inst.getOperand(1)); 8279 TmpInst.addOperand(Inst.getOperand(2)); 8280 TmpInst.addOperand(Inst.getOperand(3)); 8281 Inst = TmpInst; 8286 if (Inst.getOperand(1).getReg() != ARM::PC || 8287 Inst.getOperand(5).getReg() != 0 || 8288 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 8288 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 8292 TmpInst.addOperand(Inst.getOperand(0)); 8293 if (Inst.getOperand(2).isImm()) { 8296 unsigned Enc = Inst.getOperand(2).getImm(); 8305 const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); 8316 TmpInst.addOperand(Inst.getOperand(3)); 8317 TmpInst.addOperand(Inst.getOperand(4)); 8318 Inst = TmpInst; 8324 if (Inst.getOperand(1).getImm() > 0 && 8325 Inst.getOperand(1).getImm() <= 0xff && 8327 Inst.setOpcode(ARM::tLDRpci); 8329 Inst.setOpcode(ARM::t2LDRpci); 8332 Inst.setOpcode(ARM::t2LDRBpci); 8335 Inst.setOpcode(ARM::t2LDRHpci); 8338 Inst.setOpcode(ARM::t2LDRSBpci); 8341 Inst.setOpcode(ARM::t2LDRSHpci); 8350 if (Inst.getOpcode() == ARM::LDRConstPool) 8352 else if (Inst.getOpcode() == ARM::tLDRConstPool) 8354 else if (Inst.getOpcode() == ARM::t2LDRConstPool) 8363 Inst.getOperand(0).getReg() != ARM::PC && 8364 Inst.getOperand(0).getReg() != ARM::SP) { 8369 if (Inst.getOpcode() == ARM::LDRConstPool) { 8406 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8408 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8409 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8412 Inst = TmpInst; 8420 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8424 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8425 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8426 Inst = TmpInst; 8437 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8438 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8439 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8440 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8441 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8442 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8443 TmpInst.addOperand(Inst.getOperand(1)); // lane 8444 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8445 TmpInst.addOperand(Inst.getOperand(6)); 8446 Inst = TmpInst; 8459 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8460 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8461 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8462 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8463 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8464 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8465 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8467 TmpInst.addOperand(Inst.getOperand(1)); // lane 8468 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8469 TmpInst.addOperand(Inst.getOperand(6)); 8470 Inst = TmpInst; 8483 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8484 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8485 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8486 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8487 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8488 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8489 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8491 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8493 TmpInst.addOperand(Inst.getOperand(1)); // lane 8494 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8495 TmpInst.addOperand(Inst.getOperand(6)); 8496 Inst = TmpInst; 8509 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8510 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8511 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8512 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8513 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8514 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8515 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8517 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8521 TmpInst.addOperand(Inst.getOperand(1)); // lane 8522 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8523 TmpInst.addOperand(Inst.getOperand(6)); 8524 Inst = TmpInst; 8535 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8536 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8537 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8538 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8540 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8541 TmpInst.addOperand(Inst.getOperand(1)); // lane 8542 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8543 TmpInst.addOperand(Inst.getOperand(5)); 8544 Inst = TmpInst; 8557 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8558 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8559 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8560 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8562 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8563 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8565 TmpInst.addOperand(Inst.getOperand(1)); // lane 8566 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8567 TmpInst.addOperand(Inst.getOperand(5)); 8568 Inst = TmpInst; 8581 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8582 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8583 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8584 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8586 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8587 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8589 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8591 TmpInst.addOperand(Inst.getOperand(1)); // lane 8592 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8593 TmpInst.addOperand(Inst.getOperand(5)); 8594 Inst = TmpInst; 8607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8608 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8609 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8610 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8612 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8613 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8615 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8619 TmpInst.addOperand(Inst.getOperand(1)); // lane 8620 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8621 TmpInst.addOperand(Inst.getOperand(5)); 8622 Inst = TmpInst; 8633 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8634 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8635 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8636 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8637 TmpInst.addOperand(Inst.getOperand(1)); // lane 8638 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8639 TmpInst.addOperand(Inst.getOperand(5)); 8640 Inst = TmpInst; 8653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8654 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8655 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8656 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8657 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8659 TmpInst.addOperand(Inst.getOperand(1)); // lane 8660 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8661 TmpInst.addOperand(Inst.getOperand(5)); 8662 Inst = TmpInst; 8675 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8676 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8677 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8678 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8679 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8681 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8683 TmpInst.addOperand(Inst.getOperand(1)); // lane 8684 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8685 TmpInst.addOperand(Inst.getOperand(5)); 8686 Inst = TmpInst; 8699 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8700 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8701 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8702 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8703 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8705 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8707 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8709 TmpInst.addOperand(Inst.getOperand(1)); // lane 8710 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8711 TmpInst.addOperand(Inst.getOperand(5)); 8712 Inst = TmpInst; 8724 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8725 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8726 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8727 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8728 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8729 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8730 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8731 TmpInst.addOperand(Inst.getOperand(1)); // lane 8732 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8733 TmpInst.addOperand(Inst.getOperand(6)); 8734 Inst = TmpInst; 8747 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8748 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8749 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8751 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8752 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8753 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8754 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8755 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8756 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8758 TmpInst.addOperand(Inst.getOperand(1)); // lane 8759 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8760 TmpInst.addOperand(Inst.getOperand(6)); 8761 Inst = TmpInst; 8774 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8775 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8776 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8778 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8780 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8781 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8782 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8783 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8784 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8787 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8789 TmpInst.addOperand(Inst.getOperand(1)); // lane 8790 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8791 TmpInst.addOperand(Inst.getOperand(6)); 8792 Inst = TmpInst; 8805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8806 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8811 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8813 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8814 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8815 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8816 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8817 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8818 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8822 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8824 TmpInst.addOperand(Inst.getOperand(1)); // lane 8825 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8826 TmpInst.addOperand(Inst.getOperand(6)); 8827 Inst = TmpInst; 8838 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8839 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8840 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8841 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8842 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8844 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8845 TmpInst.addOperand(Inst.getOperand(1)); // lane 8846 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8847 TmpInst.addOperand(Inst.getOperand(5)); 8848 Inst = TmpInst; 8861 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8862 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8863 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8865 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8866 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8867 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8869 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8870 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8872 TmpInst.addOperand(Inst.getOperand(1)); // lane 8873 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8874 TmpInst.addOperand(Inst.getOperand(5)); 8875 Inst = TmpInst; 8888 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8889 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8890 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8892 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8894 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8895 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8896 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8898 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8899 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8901 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8903 TmpInst.addOperand(Inst.getOperand(1)); // lane 8904 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8905 TmpInst.addOperand(Inst.getOperand(5)); 8906 Inst = TmpInst; 8919 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8920 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8925 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8927 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8928 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8929 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8931 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8932 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8934 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8936 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8938 TmpInst.addOperand(Inst.getOperand(1)); // lane 8939 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8940 TmpInst.addOperand(Inst.getOperand(5)); 8941 Inst = TmpInst; 8952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8953 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8954 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8955 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8956 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8957 TmpInst.addOperand(Inst.getOperand(1)); // lane 8958 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8959 TmpInst.addOperand(Inst.getOperand(5)); 8960 Inst = TmpInst; 8973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8974 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8975 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8977 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8978 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8979 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8980 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8982 TmpInst.addOperand(Inst.getOperand(1)); // lane 8983 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8984 TmpInst.addOperand(Inst.getOperand(5)); 8985 Inst = TmpInst; 8998 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8999 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9002 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9004 TmpInst.addOperand(Inst.getOperand(2)); // Rn 9005 TmpInst.addOperand(Inst.getOperand(3)); // alignment 9006 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 9007 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9009 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9011 TmpInst.addOperand(Inst.getOperand(1)); // lane 9012 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9013 TmpInst.addOperand(Inst.getOperand(5)); 9014 Inst = TmpInst; 9027 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9028 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9029 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9031 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9033 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9035 TmpInst.addOperand(Inst.getOperand(2)); // Rn 9036 TmpInst.addOperand(Inst.getOperand(3)); // alignment 9037 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 9038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9040 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9044 TmpInst.addOperand(Inst.getOperand(1)); // lane 9045 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9046 TmpInst.addOperand(Inst.getOperand(5)); 9047 Inst = TmpInst; 9060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9061 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9062 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9064 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9066 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9067 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9068 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9069 TmpInst.addOperand(Inst.getOperand(4)); 9070 Inst = TmpInst; 9082 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9083 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9084 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9086 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9088 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9089 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9090 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9092 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9093 TmpInst.addOperand(Inst.getOperand(4)); 9094 Inst = TmpInst; 9106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9107 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9108 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9110 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9112 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9113 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9114 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9115 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9116 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9117 TmpInst.addOperand(Inst.getOperand(5)); 9118 Inst = TmpInst; 9131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9132 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9133 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9135 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9137 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9138 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9139 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9140 TmpInst.addOperand(Inst.getOperand(4)); 9141 Inst = TmpInst; 9153 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9154 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9155 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9157 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9159 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9160 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9161 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9163 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9164 TmpInst.addOperand(Inst.getOperand(4)); 9165 Inst = TmpInst; 9177 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9178 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9179 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9181 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9183 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9184 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9185 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9186 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9187 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9188 TmpInst.addOperand(Inst.getOperand(5)); 9189 Inst = TmpInst; 9202 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9203 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9204 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9206 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9208 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9210 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9211 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9212 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9213 TmpInst.addOperand(Inst.getOperand(4)); 9214 Inst = TmpInst; 9226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9227 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9228 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9232 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9234 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9235 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9236 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9238 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9239 TmpInst.addOperand(Inst.getOperand(4)); 9240 Inst = TmpInst; 9252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9253 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9254 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9258 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9260 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9261 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9262 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9263 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9265 TmpInst.addOperand(Inst.getOperand(5)); 9266 Inst = TmpInst; 9279 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9280 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9281 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9283 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9285 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9287 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9288 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9289 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9290 TmpInst.addOperand(Inst.getOperand(4)); 9291 Inst = TmpInst; 9303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9304 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9307 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9309 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9311 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9312 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9313 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9315 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9316 TmpInst.addOperand(Inst.getOperand(4)); 9317 Inst = TmpInst; 9329 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9330 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9331 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9333 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9335 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9337 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9338 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9339 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9340 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9341 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9342 TmpInst.addOperand(Inst.getOperand(5)); 9343 Inst = TmpInst; 9356 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9357 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9358 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9359 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9360 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9362 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9364 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9365 TmpInst.addOperand(Inst.getOperand(4)); 9366 Inst = TmpInst; 9378 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9379 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9380 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9381 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9383 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9386 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9388 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9389 TmpInst.addOperand(Inst.getOperand(4)); 9390 Inst = TmpInst; 9402 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9403 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9404 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9405 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9406 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9407 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9408 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9410 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9412 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9413 TmpInst.addOperand(Inst.getOperand(5)); 9414 Inst = TmpInst; 9427 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9428 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9429 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9430 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9431 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9435 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9437 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9438 TmpInst.addOperand(Inst.getOperand(4)); 9439 Inst = TmpInst; 9451 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9452 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9454 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9456 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9457 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9459 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9461 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9463 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9464 TmpInst.addOperand(Inst.getOperand(4)); 9465 Inst = TmpInst; 9477 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9478 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9479 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9480 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9481 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9482 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9483 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9485 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9487 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9489 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9490 TmpInst.addOperand(Inst.getOperand(5)); 9491 Inst = TmpInst; 9499 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9500 isARMLowRegister(Inst.getOperand(1).getReg()) && 9501 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9504 switch (Inst.getOpcode()) { 9513 TmpInst.addOperand(Inst.getOperand(0)); 9514 TmpInst.addOperand(Inst.getOperand(5)); 9515 TmpInst.addOperand(Inst.getOperand(1)); 9516 TmpInst.addOperand(Inst.getOperand(2)); 9517 TmpInst.addOperand(Inst.getOperand(3)); 9518 TmpInst.addOperand(Inst.getOperand(4)); 9519 Inst = TmpInst; 9531 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9532 isARMLowRegister(Inst.getOperand(1).getReg()) && 9533 isARMLowRegister(Inst.getOperand(2).getReg()) && 9534 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 9534 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 9535 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && 9540 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 9548 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9551 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 9552 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9553 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9554 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9555 TmpInst.addOperand(Inst.getOperand(5)); 9558 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 9559 Inst = TmpInst; 9568 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9569 isARMLowRegister(Inst.getOperand(1).getReg()) && 9570 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && 9575 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 9576 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 9601 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9604 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 9605 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9608 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9609 TmpInst.addOperand(Inst.getOperand(4)); 9612 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 9613 Inst = TmpInst; 9622 switch(Inst.getOpcode()) { 9632 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9633 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9634 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9636 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9637 TmpInst.addOperand(Inst.getOperand(4)); 9638 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9639 Inst = TmpInst; 9647 switch(Inst.getOpcode()) { 9655 unsigned Amt = Inst.getOperand(2).getImm(); 9663 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9664 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9667 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9668 TmpInst.addOperand(Inst.getOperand(4)); 9669 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9670 Inst = TmpInst; 9677 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9678 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9680 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9681 TmpInst.addOperand(Inst.getOperand(3)); 9682 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 9683 Inst = TmpInst; 9689 if (Inst.getNumOperands() != 5) 9693 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9694 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9695 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9697 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9698 TmpInst.addOperand(Inst.getOperand(3)); 9699 Inst = TmpInst; 9705 if (Inst.getNumOperands() != 5) 9709 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9710 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9711 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9713 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9714 TmpInst.addOperand(Inst.getOperand(3)); 9715 Inst = TmpInst; 9722 Inst.getNumOperands() == 5) { 9725 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9726 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9727 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9730 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9731 TmpInst.addOperand(Inst.getOperand(3)); 9732 Inst = TmpInst; 9740 Inst.getNumOperands() == 5) { 9743 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9744 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9745 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 9747 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9748 TmpInst.addOperand(Inst.getOperand(3)); 9749 Inst = TmpInst; 9756 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9758 Inst.setOpcode(ARM::t2ADDri); 9759 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9765 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9767 Inst.setOpcode(ARM::t2SUBri); 9768 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9775 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9776 Inst.setOpcode(ARM::tADDi3); 9785 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9786 Inst.setOpcode(ARM::tSUBi3); 9796 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 9796 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 9797 !isARMLowRegister(Inst.getOperand(0).getReg()) || 9798 (Inst.getOperand(2).isImm() && 9799 (unsigned)Inst.getOperand(2).getImm() > 255) || 9800 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || 9804 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 9806 TmpInst.addOperand(Inst.getOperand(0)); 9807 TmpInst.addOperand(Inst.getOperand(5)); 9808 TmpInst.addOperand(Inst.getOperand(0)); 9809 TmpInst.addOperand(Inst.getOperand(2)); 9810 TmpInst.addOperand(Inst.getOperand(3)); 9811 TmpInst.addOperand(Inst.getOperand(4)); 9812 Inst = TmpInst; 9822 auto DestReg = Inst.getOperand(0).getReg(); 9823 bool Transform = DestReg == Inst.getOperand(1).getReg(); 9824 if (!Transform && DestReg == Inst.getOperand(2).getReg()) { 9829 Inst.getOperand(5).getReg() != 0 || 9834 TmpInst.addOperand(Inst.getOperand(0)); 9835 TmpInst.addOperand(Inst.getOperand(0)); 9836 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); 9837 TmpInst.addOperand(Inst.getOperand(3)); 9838 TmpInst.addOperand(Inst.getOperand(4)); 9839 Inst = TmpInst; 9845 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 9845 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 9846 Inst.setOpcode(ARM::t2ADDrr); 9847 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9853 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 9854 Inst.setOpcode(ARM::tBcc); 9860 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 9861 Inst.setOpcode(ARM::t2Bcc); 9867 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 9868 Inst.setOpcode(ARM::t2B); 9874 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 9875 Inst.setOpcode(ARM::tB); 9884 unsigned Rn = Inst.getOperand(0).getReg(); 9889 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 9894 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 9898 Inst.insert(Inst.begin(), 9898 Inst.insert(Inst.begin(), 9899 MCOperand::createReg(Inst.getOperand(0).getReg())); 9908 unsigned Rn = Inst.getOperand(0).getReg(); 9910 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 9913 Inst.setOpcode(ARM::t2STMIA_UPD); 9923 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 9926 Inst.setOpcode(ARM::t2LDMIA_UPD); 9928 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9928 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9929 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9929 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9934 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 9937 Inst.setOpcode(ARM::t2STMDB_UPD); 9939 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9939 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9940 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9940 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9946 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9947 (Inst.getOperand(1).isImm() && 9948 (unsigned)Inst.getOperand(1).getImm() <= 255) && 9949 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9954 TmpInst.addOperand(Inst.getOperand(0)); 9955 TmpInst.addOperand(Inst.getOperand(4)); 9956 TmpInst.addOperand(Inst.getOperand(1)); 9957 TmpInst.addOperand(Inst.getOperand(2)); 9958 TmpInst.addOperand(Inst.getOperand(3)); 9959 Inst = TmpInst; 9967 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9968 isARMLowRegister(Inst.getOperand(1).getReg()) && 9969 Inst.getOperand(2).getImm() == ARMCC::AL && 9970 Inst.getOperand(4).getReg() == ARM::CPSR && 9974 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 9975 TmpInst.addOperand(Inst.getOperand(0)); 9976 TmpInst.addOperand(Inst.getOperand(1)); 9977 TmpInst.addOperand(Inst.getOperand(2)); 9978 TmpInst.addOperand(Inst.getOperand(3)); 9979 Inst = TmpInst; 9990 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9991 isARMLowRegister(Inst.getOperand(1).getReg()) && 9992 Inst.getOperand(2).getImm() == 0 && 9995 switch (Inst.getOpcode()) { 10005 TmpInst.addOperand(Inst.getOperand(0)); 10006 TmpInst.addOperand(Inst.getOperand(1)); 10007 TmpInst.addOperand(Inst.getOperand(3)); 10008 TmpInst.addOperand(Inst.getOperand(4)); 10009 Inst = TmpInst; 10015 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 10019 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 10023 TmpInst.addOperand(Inst.getOperand(0)); 10024 TmpInst.addOperand(Inst.getOperand(1)); 10025 TmpInst.addOperand(Inst.getOperand(3)); 10026 TmpInst.addOperand(Inst.getOperand(4)); 10027 TmpInst.addOperand(Inst.getOperand(5)); 10028 Inst = TmpInst; 10040 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 10042 switch (Inst.getOpcode()) { 10053 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 10057 TmpInst.addOperand(Inst.getOperand(0)); 10058 TmpInst.addOperand(Inst.getOperand(1)); 10059 TmpInst.addOperand(Inst.getOperand(2)); 10060 TmpInst.addOperand(Inst.getOperand(4)); 10061 TmpInst.addOperand(Inst.getOperand(5)); 10062 TmpInst.addOperand(Inst.getOperand(6)); 10063 Inst = TmpInst; 10073 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()), 10074 Inst.getOperand(1).getImm()); 10084 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10085 isARMLowRegister(Inst.getOperand(2).getReg())) && 10086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 10086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 10087 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10090 switch (Inst.getOpcode()) { 10101 TmpInst.addOperand(Inst.getOperand(0)); 10102 TmpInst.addOperand(Inst.getOperand(5)); 10103 TmpInst.addOperand(Inst.getOperand(1)); 10104 TmpInst.addOperand(Inst.getOperand(2)); 10105 TmpInst.addOperand(Inst.getOperand(3)); 10106 TmpInst.addOperand(Inst.getOperand(4)); 10107 Inst = TmpInst; 10119 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10120 isARMLowRegister(Inst.getOperand(2).getReg())) && 10121 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 10121 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 10122 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 10122 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 10123 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10126 switch (Inst.getOpcode()) { 10135 TmpInst.addOperand(Inst.getOperand(0)); 10136 TmpInst.addOperand(Inst.getOperand(5)); 10137 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 10137 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 10138 TmpInst.addOperand(Inst.getOperand(1)); 10139 TmpInst.addOperand(Inst.getOperand(2)); 10141 TmpInst.addOperand(Inst.getOperand(2)); 10142 TmpInst.addOperand(Inst.getOperand(1)); 10144 TmpInst.addOperand(Inst.getOperand(3)); 10145 TmpInst.addOperand(Inst.getOperand(4)); 10146 Inst = TmpInst; 10174 MCOperand &MO = Inst.getOperand(0);