reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
817 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/ARM/ARMInstructionSelector.cpp493 (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi)) 579 BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode)) 583 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) 589 TII.get(Helper.ReadFlagsOpcode)) 591 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) 597 TII.get(Helper.SelectResultOpcode)) 602 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) 676 MIB->setDesc(TII.get(Opc)); 694 TII.get(Opcodes.LOAD32)) 701 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI)) 708 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 714 MIB->setDesc(TII.get(Opc)); 715 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 722 TII.get(Opcodes.MOVi32imm), Offset); 727 TII.get(Opcodes.ConstPoolLoad), Offset); 730 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI)) 734 MIB->setDesc(TII.get(Opcodes.ADDrr)); 741 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 746 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); 749 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); 755 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); 757 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); 763 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 776 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri)) 780 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) 791 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr)) 796 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) 806 MIB->setDesc(TII.get(ARM::MOVsr)); 809 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); 846 return selectCopy(I, TII, MRI, TRI, RBI); 872 I.setDesc(TII.get(Opcodes.AND)); 884 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB)) 890 if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI)) 900 I.setDesc(TII.get(NewOpc)); 933 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) 938 if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI)) 956 I.setDesc(TII.get(COPY)); 957 return selectCopy(I, TII, MRI, TRI, RBI); 982 I.setDesc(TII.get(ARM::MOVi)); 997 MIB->setDesc(TII.get(LoadOpcode)); 1028 I.setDesc(TII.get(COPY)); 1029 return selectCopy(I, TII, MRI, TRI, RBI); 1065 I.setDesc(TII.get(Opcodes.ADDrr)); 1071 I.setDesc(TII.get(Opcodes.ADDri)); 1105 auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND)) 1111 if (!constrainSelectedInstRegOperands(*AndI, TII, TRI, RBI)) 1115 I.setDesc(TII.get(NewOpc)); 1124 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) 1129 if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI)) 1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri)) 1145 if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI)) 1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc)) 1153 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) 1159 I.setDesc(TII.get(PHI)); 1173 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);