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reference to multiple definitions → definitions
unreferenced

References

lib/Target/ARM/ARMInstructionSelector.cpp
  346     return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
  346     return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
  349     return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
  349     return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
  363       return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
  363       return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
  365       return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
  365       return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
  367       return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
  367       return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
  493   (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi))
  673                                   : Opcodes.MOV_ga_pcrel)
  675                                   : Opcodes.LDRLIT_ga_pcrel);
  694                                TII.get(Opcodes.LOAD32))
  713     unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
  713     unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
  722                           TII.get(Opcodes.MOVi32imm), Offset);
  727                           TII.get(Opcodes.ConstPoolLoad), Offset);
  734     MIB->setDesc(TII.get(Opcodes.ADDrr));
  746       MIB->setDesc(TII.get(Opcodes.MOVi32imm));
  749       MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
  755       MIB->setDesc(TII.get(Opcodes.MOVi32imm));
  757       MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
  776   auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
  791   auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
  872       I.setDesc(TII.get(Opcodes.AND));
  884             BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB))
 1034     CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
 1035                         Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
 1054                         Opcodes.MOVCCi, ARM::FPRRegBankID, Size);
 1065     I.setDesc(TII.get(Opcodes.ADDrr));
 1071     I.setDesc(TII.get(Opcodes.ADDri));
 1097     if (ValSize == 1 && NewOpc == Opcodes.STORE8) {
 1105       auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND))
 1141         BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
 1150         BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))