reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
132 isThumb2 = AFI->isThumbFunction(); 472 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; 473 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : 485 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 488 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; 489 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : 518 if (isThumb2) 546 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass 566 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; 568 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; 592 if (isThumb2) { 625 if (isThumb2) 674 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 830 if (needsLowering && isThumb2) 849 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass 852 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 927 if (isThumb2) { 940 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 946 if (isThumb2) { 955 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 961 if (isThumb2) { 969 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 977 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; 978 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 1063 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass 1065 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; 1074 if (isThumb2) { 1087 if (isThumb2) { 1101 if (isThumb2) { 1120 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; 1265 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1275 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1288 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1313 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1326 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1337 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; 1338 assert(isThumb2 || Subtarget->hasV4TOps()); 1382 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1411 if (isThumb2) { 1484 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1485 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass 1639 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1649 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1659 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; 1660 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; 1662 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; 1664 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1666 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; 1761 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; 1764 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; 1767 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; 2179 return isThumb2 ? ARM::tBLXr : ARM::BLX; 2181 return isThumb2 ? ARM::tBL : ARM::BL; 2268 if (isThumb2) 2410 if(isThumb2) 2493 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; 2494 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass 2685 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; 2686 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; 2687 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt]; 2698 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi; 2767 if (isThumb2) 2927 if (FLE.Opc[isThumb2] == MI->getOpcode() && 2968 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;