reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
835 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 839 .addReg(SrcReg, getKillRegState(KillSrc)) 846 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 855 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64()) 857 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 862 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 864 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 878 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 882 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 887 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { 891 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { 895 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { 899 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { 903 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { 908 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { 913 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { 918 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && 923 } else if (SrcReg == ARM::CPSR) { 927 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget); 930 assert(ARM::GPRRegClass.contains(SrcReg)); 932 .addReg(SrcReg, getKillRegState(KillSrc)) 935 } else if (SrcReg == ARM::VPR) { 938 .addReg(SrcReg, getKillRegState(KillSrc)) 942 assert(ARM::GPRRegClass.contains(SrcReg)); 944 .addReg(SrcReg, getKillRegState(KillSrc)) 947 } else if (SrcReg == ARM::FPSCR_NZCV) { 950 .addReg(SrcReg, getKillRegState(KillSrc)) 961 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 970 Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); 993 Mov->addRegisterKilled(SrcReg, TRI);