reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
3334 switch (MI.getOpcode()) { 3336 const MCInstrDesc &Desc = MI.getDesc(); 3346 unsigned ShOpVal = MI.getOperand(3).getImm(); 3359 if (!MI.getOperand(2).getReg()) 3362 unsigned ShOpVal = MI.getOperand(3).getImm(); 3375 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2; 3379 Register Rt = MI.getOperand(0).getReg(); 3380 Register Rm = MI.getOperand(3).getReg(); 3386 Register Rt = MI.getOperand(0).getReg(); 3387 Register Rm = MI.getOperand(3).getReg(); 3390 unsigned ShOpVal = MI.getOperand(4).getImm(); 3403 unsigned ShOpVal = MI.getOperand(4).getImm(); 3416 Register Rt = MI.getOperand(0).getReg(); 3417 Register Rm = MI.getOperand(3).getReg(); 3422 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2; 3428 Register Rt = MI.getOperand(0).getReg(); 3429 Register Rm = MI.getOperand(3).getReg(); 3448 Register Rm = MI.getOperand(3).getReg(); 3451 Register Rt = MI.getOperand(0).getReg(); 3454 unsigned ShOpVal = MI.getOperand(4).getImm(); 3466 Register Rt = MI.getOperand(0).getReg(); 3467 Register Rn = MI.getOperand(2).getReg(); 3468 Register Rm = MI.getOperand(3).getReg(); 3470 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4 3476 Register Rm = MI.getOperand(3).getReg(); 3478 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4 3492 Register Rt = MI.getOperand(0).getReg(); 3493 Register Rn = MI.getOperand(3).getReg(); 3494 Register Rm = MI.getOperand(4).getReg(); 3496 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5 3502 Register Rt = MI.getOperand(0).getReg(); 3503 Register Rn = MI.getOperand(3).getReg(); 3508 Register Rm = MI.getOperand(4).getReg(); 3510 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5 3539 Register Rt = MI.getOperand(0).getReg(); 3540 Register Rn = MI.getOperand(2).getReg();