reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1568 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) { 1571 expandLoadStackGuard(MI); 1572 MI.getParent()->erase(MI); 1572 MI.getParent()->erase(MI); 1576 if (MI.getOpcode() == ARM::MEMCPY) { 1577 expandMEMCPY(MI); 1585 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || !Subtarget.hasFP64()) 1590 Register DstRegS = MI.getOperand(0).getReg(); 1591 Register SrcRegS = MI.getOperand(1).getReg(); 1606 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI)) 1606 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI)) 1610 if (MI.getOperand(0).isDead()) 1614 LLVM_DEBUG(dbgs() << "widening: " << MI); 1615 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); 1615 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); 1619 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); 1621 MI.RemoveOperand(ImpDefIdx); 1624 MI.setDesc(get(ARM::VMOVD)); 1625 MI.getOperand(0).setReg(DstRegD); 1626 MI.getOperand(1).setReg(SrcRegD); 1633 MI.getOperand(1).setIsUndef(); 1638 if (MI.getOperand(1).isKill()) { 1639 MI.getOperand(1).setIsKill(false); 1640 MI.addRegisterKilled(SrcRegS, TRI, true); 1643 LLVM_DEBUG(dbgs() << "replaced by: " << MI);