reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/ARM/ARMBaseInstrInfo.cpp
 1285       BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
 1295       BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
 1301       BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
 1307       BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
 1317       BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
 1327         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
 1328         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
 1338         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
 1339         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
 1342       if (Register::isPhysicalRegister(DestReg))
 1343         MIB.addReg(DestReg, RegState::ImplicitDefine);
 1350         BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
 1356         BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
 1363       auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
 1375         BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
 1385         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
 1386         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
 1387         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
 1388         if (Register::isPhysicalRegister(DestReg))
 1389           MIB.addReg(DestReg, RegState::ImplicitDefine);
 1398         BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
 1408         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
 1409         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
 1410         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
 1411         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
 1412         if (Register::isPhysicalRegister(DestReg))
 1413           MIB.addReg(DestReg, RegState::ImplicitDefine);
 1424       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
 1425       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
 1426       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
 1427       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
 1428       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
 1429       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
 1430       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
 1431       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
 1432       if (Register::isPhysicalRegister(DestReg))
 1433         MIB.addReg(DestReg, RegState::ImplicitDefine);