reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
569 if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) { 578 MachineOperand &Src = MI.getOperand(1); 580 Register::isPhysicalRegister(MI.getOperand(0).getReg())) { 583 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); 590 if (ST.hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 || 591 MI.getOpcode() == AMDGPU::COPY)) { 592 if (auto *NextMI = matchSwap(MI, MRI, TII)) { 605 if (MI.getOpcode() == AMDGPU::S_NOP && 613 uint8_t Nop0 = MI.getOperand(0).getImm() + 1; 619 MI.eraseFromParent(); 630 if (MI.getOpcode() == AMDGPU::S_ADD_I32 || 631 MI.getOpcode() == AMDGPU::S_MUL_I32) { 632 const MachineOperand *Dest = &MI.getOperand(0); 633 MachineOperand *Src0 = &MI.getOperand(1); 634 MachineOperand *Src1 = &MI.getOperand(2); 637 if (TII->commuteInstruction(MI, false, 1, 2)) 652 unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? 655 MI.setDesc(TII->get(Opc)); 656 MI.tieOperands(0, 1); 662 if (MI.isCompare() && TII->isSOPC(MI)) { 662 if (MI.isCompare() && TII->isSOPC(MI)) { 663 shrinkScalarCompare(TII, MI); 668 if (MI.getOpcode() == AMDGPU::S_MOV_B32) { 669 const MachineOperand &Dst = MI.getOperand(0); 670 MachineOperand &Src = MI.getOperand(1); 675 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); 677 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); 686 if (MI.getOpcode() == AMDGPU::S_AND_B32 || 687 MI.getOpcode() == AMDGPU::S_OR_B32 || 688 MI.getOpcode() == AMDGPU::S_XOR_B32) { 689 if (shrinkScalarLogicOp(ST, MRI, TII, MI)) 693 if (TII->isMIMG(MI.getOpcode()) && 697 shrinkMIMG(MI); 701 if (!TII->hasVALU32BitEncoding(MI.getOpcode())) 704 if (!TII->canShrink(MI, MRI)) { 707 if (!MI.isCommutable() || !TII->commuteInstruction(MI) || 707 if (!MI.isCommutable() || !TII->commuteInstruction(MI) || 708 !TII->canShrink(MI, MRI)) 714 if (!TII->hasVALU32BitEncoding(MI.getOpcode())) 717 int Op32 = AMDGPU::getVOPe32(MI.getOpcode()); 720 Register DstReg = MI.getOperand(0).getReg(); 730 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, VCCReg); 741 TII->getNamedOperand(MI, AMDGPU::OpName::src2); 754 const MachineOperand *SDst = TII->getNamedOperand(MI, 758 const MachineOperand *Src2 = TII->getNamedOperand(MI, 783 LLVM_DEBUG(dbgs() << "Shrinking " << MI); 785 MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32); 789 copyExtraImplicitOps(*Inst32, MF, MI); 791 MI.eraseFromParent();