reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  792   if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  707         if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) &&
  709             (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
  776           !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) {
  787         if (!TRI->isSGPRReg(*MRI, Use.getReg()) &&
lib/Target/AMDGPU/SIFixupVectorISel.cpp
  141       if (!TRI->isSGPRReg(MRI, BaseReg))
lib/Target/AMDGPU/SIFoldOperands.cpp
  731             if (TRI->isSGPRReg(*MRI, Src.Reg)) {
  800       if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
 1010     bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
lib/Target/AMDGPU/SIISelLowering.cpp
10414             !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg()))
10838         return !TRI.isSGPRReg(MRI, Reg);
10843         if (!TRI.isSGPRReg(MRI, Reg))
10855       return !TRI.isSGPRReg(MRI, Reg);
11030             if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg))
lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  482   } else if (TRI->isSGPRReg(MRIA, Op.getReg())) {
lib/Target/AMDGPU/SIInstrInfo.cpp
 2657        !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
 2792     if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
 4027       Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
 5496   if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
lib/Target/AMDGPU/SIInstrInfo.h
  675     return !RI.isSGPRReg(MRI, Dest);
lib/Target/AMDGPU/SILowerI1Copies.cpp
  104     return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) &&
lib/Target/AMDGPU/SIPeepholeSDWA.cpp
 1187         TRI->isSGPRReg(*MRI, Op.getReg())) {
lib/Target/AMDGPU/SIWholeQuadMode.cpp
  545         if (TRI->isSGPRReg(*MRI, Op.getReg())) {