reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2650 if (!RC || SIRI->isSGPRClass(RC))
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1419 IsSgpr = TRI.isSGPRClass(RC);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 172 return TRI->isSGPRClass(&RC) ? AMDGPU::SGPRRegBank : AMDGPU::VGPRRegBank;
lib/Target/AMDGPU/GCNHazardRecognizer.cpp970 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { 1055 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))lib/Target/AMDGPU/GCNRegPressure.cpp
90 return STI->isSGPRClass(RC) ?
lib/Target/AMDGPU/SIFixSGPRCopies.cpp190 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && 197 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && 246 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) 292 assert(TRI->isSGPRClass(SrcRC) && 679 if (TRI->isSGPRClass(DstRC) && 795 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && 818 if (TRI->isSGPRClass(RC))lib/Target/AMDGPU/SIFoldOperands.cpp
626 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
lib/Target/AMDGPU/SIISelLowering.cpp3347 if (!TII->getRegisterInfo().isSGPRClass(IdxRC)) 10943 if (!TRI->isSGPRClass(RC) && !isDivergent) 10945 else if (TRI->isSGPRClass(RC) && isDivergent) 11032 else if (SIRI->isSGPRClass(RC))lib/Target/AMDGPU/SIInstrInfo.cpp
683 if (RI.isSGPRClass(RC)) { 693 if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) { 787 if (RI.isSGPRClass(RegClass)) { 971 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; 972 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { 974 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { 1063 if (RI.isSGPRClass(RC)) { 1191 if (RI.isSGPRClass(RC)) { 2150 return RI.isSGPRClass(RC); 2374 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) 2377 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) 2441 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || 2444 RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))) 2458 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || 2460 RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) 3115 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); 3837 else if (RI.isSGPRClass(RC)) 4140 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { 4146 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { 4192 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) 4261 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { 4266 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) { 4310 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) && 4557 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { 4652 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { 4658 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) { 5191 RI.isSGPRClass(MRI.getRegClass(Src0.getReg())); 5193 RI.isSGPRClass(MRI.getRegClass(Src1.getReg())); 5815 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); 5822 if (RI.isSGPRClass(RegRC))lib/Target/AMDGPU/SIRegisterInfo.cpp
1411 if (isSGPRClass(RC)) {
lib/Target/AMDGPU/SIRegisterInfo.h135 return isSGPRClass(getRegClass(RCID)); 144 return isSGPRClass(RC); 212 return !isSGPRClass(RC);