reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/SIRegisterInfo.h

  151   bool hasAGPRs(const TargetRegisterClass *RC) const;

References

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  368     if (TRI->hasAGPRs(TRI->getRegClassForReg(*MRI, R)))

lib/Target/AMDGPU/GCNRegPressure.cpp

   92     STI->hasAGPRs(RC) ?

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  285   bool IsAGPR = TRI->hasAGPRs(DstRC);
  804   if (AllAGPRUses && numVGPRUses && !TRI->hasAGPRs(RC0)) {

lib/Target/AMDGPU/SIInstrInfo.cpp

  697   } else if (RI.hasAGPRs(RC)) {
  700   } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) {
  968   if (RI.hasAGPRs(DstRC))
 1091   unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize)
 1096   if (RI.hasAGPRs(RC)) {
 1212   unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
 1215   if (RI.hasAGPRs(RC)) {
 4186     if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
 4218   if (RI.hasAGPRs(VRC)) {
 4563           VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
 4567           VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
 5750     if (RI.hasAGPRs(SrcRC)) {
 5751       if (RI.hasAGPRs(NewDstRC))

lib/Target/AMDGPU/SIRegisterInfo.cpp

  647     hasAGPRs(RC) ? TII->getNamedOperand(*MI, AMDGPU::OpName::tmp)->getReg()
 1431   } else if (hasAGPRs(RC)) {
 1709   return hasAGPRs(RC);

lib/Target/AMDGPU/SIRegisterInfo.h

  130     return !hasVGPRs(RC) && !hasAGPRs(RC);
  155     return hasVGPRs(RC) || hasAGPRs(RC);