reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/SIRegisterInfo.h

  277   const TargetRegisterClass *getRegClass(unsigned RCID) const;

References

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  574     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
  579         Subtarget->getRegisterInfo()->getRegClass(RCID);

lib/Target/AMDGPU/SIFoldOperands.cpp

  842     TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);

lib/Target/AMDGPU/SIISelLowering.cpp

 3285   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 3761     const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);

lib/Target/AMDGPU/SIInstrInfo.cpp

  822     RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 3292       const TargetRegisterClass *RC = RI.getRegClass(RegClass);
 3821   return RI.getRegClass(RCID);
 3832   const TargetRegisterClass *RC = RI.getRegClass(RCID);
 3924   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
 3957       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
 4332   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 4413   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 4673                              RI.getRegClass(RsrcRC))) {
 4702       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 5347   const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 5814     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
 6266   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);

lib/Target/AMDGPU/SIInstrInfo.h

  812     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
 1026     return RI.getRegClass(TID.OpInfo[OpNum].RegClass);

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1390   const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

 1183        !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))

lib/Target/AMDGPU/SIRegisterInfo.h

  135     return isSGPRClass(getRegClass(RCID));