reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/SIRegisterInfo.h

  126   const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;

References

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  557       return TRI->getPhysRegClass(Reg);

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

  970       if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
 1055         if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  175                                          : TRI.getPhysRegClass(SrcReg);
  182                                          : TRI.getPhysRegClass(DstReg);

lib/Target/AMDGPU/SIInstrInfo.cpp

  482                                          : RI.getPhysRegClass(Reg);
  528   const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
  693     if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
  698     Opcode = RI.hasVGPRs(RI.getPhysRegClass(SrcReg)) ?
  700   } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) {
 2441                      RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
 2458                     RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
 3817     return RI.getPhysRegClass(Reg);
 3922                                       : RI.getPhysRegClass(Reg);

lib/Target/AMDGPU/SIRegisterInfo.cpp

  777   const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
  889   const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
 1695   return getPhysRegClass(Reg);

lib/Target/AMDGPU/SIRegisterInfo.h

  143       RC = getPhysRegClass(Reg);

lib/Target/AMDGPU/SIWholeQuadMode.cpp

  396                 TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) {
  863                                                 : TRI->getPhysRegClass(Reg);