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References

lib/Target/AMDGPU/SIModeRegister.cpp
   53   Status merge(const Status &S) const {
   53   Status merge(const Status &S) const {
   59   Status mergeUnknown(unsigned newMask) {
   65   Status intersect(const Status &S) const {
   65   Status intersect(const Status &S) const {
   72   Status delta(const Status &S) const {
   72   Status delta(const Status &S) const {
   76   bool operator==(const Status &S) const {
   80   bool operator!=(const Status &S) const { return !(*this == S); }
   82   bool isCompatible(Status &S) {
   86   bool isCombinable(Status &S) {
   95   Status Require;
   99   Status Change;
  103   Status Exit;
  107   Status Pred;
  131   Status DefaultStatus =
  150   Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
  153                     const SIInstrInfo *TII, Status InstrMode);
  170 Status SIModeRegister::getInstructionMode(MachineInstr &MI,
  193                                   const SIInstrInfo *TII, Status InstrMode) {
  237   Status IPChange;
  239     Status InstrMode = getInstructionMode(MI, TII);
  268         Status Setreg = Status(Mask, Mode);
  345   Status TmpStatus = BlockInfo[ThisBlock]->Pred.merge(BlockInfo[ThisBlock]->Change);
  367     Status Delta = BlockInfo[ThisBlock]->Pred.delta(BlockInfo[ThisBlock]->Require);