reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
 1470         TFI, CurDAG->getRegister(Info->getStackPtrOffsetReg(), MVT::i32));
 1502       Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
 1563     Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
 2028                                          ? Info->getStackPtrOffsetReg()
 2071   Register SOffset = FI.hasValue() ? Info->getStackPtrOffsetReg()
 2124                             ? Info->getStackPtrOffsetReg()
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
  133                         : FuncInfo->getStackPtrOffsetReg();
lib/Target/AMDGPU/SIFoldOperands.cpp
  595                            SOff->getReg() != MFI->getStackPtrOffsetReg()))
  605     SOff->setReg(MFI->getStackPtrOffsetReg());
lib/Target/AMDGPU/SIFrameLowering.cpp
  375         if (MFI->getScratchWaveOffsetReg() == MFI->getStackPtrOffsetReg()) {
  493   unsigned SPReg = MFI->getStackPtrOffsetReg();
  696   unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
  847     const unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
  903                       FuncInfo->getStackPtrOffsetReg(), Reg.FI.getValue());
 1072   SavedRegs.reset(MFI->getStackPtrOffsetReg());
 1118     unsigned SPReg = MFI->getStackPtrOffsetReg();
lib/Target/AMDGPU/SIISelLowering.cpp
 1933       if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
 3804     MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
 3805         .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
10686                              Info->getStackPtrOffsetReg()));
10687   if (Info->getStackPtrOffsetReg() != AMDGPU::SP_REG)
10688     MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());
lib/Target/AMDGPU/SIInstrInfo.cpp
 1082       .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
 1104      .addReg(MFI->getStackPtrOffsetReg())     // scratch_offset
 1208       .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
 1222      .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  493     StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
lib/Target/AMDGPU/SIRegisterInfo.cpp
  236   unsigned StackPtrReg = MFI->getStackPtrOffsetReg();
  402          MF->getInfo<SIMachineFunctionInfo>()->getStackPtrOffsetReg() &&
  768   assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() &&
  847         .addReg(MFI->getStackPtrOffsetReg())  // soffset
  930         .addReg(MFI->getStackPtrOffsetReg())  // soffset
 1044              MFI->getStackPtrOffsetReg());
 1074              MFI->getStackPtrOffsetReg());
 1207                MFI->getStackPtrOffsetReg());