reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
 1102                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
 1104                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
 1107                              MFI->ArgInfo.QueuePtr, 2, 0) ||
 1110                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
 1112                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
 1116                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
 1119                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
 1121                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
 1124                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
 1127                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
 1131                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
 1134                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
 1137                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
 1140                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
 1143                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
 1146                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
 1149                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
   78     ArgInfo.PrivateSegmentBuffer =
   80     ArgInfo.PrivateSegmentWaveByteOffset =
  125       ArgInfo.PrivateSegmentWaveByteOffset =
  190   ArgInfo.PrivateSegmentBuffer =
  194   return ArgInfo.PrivateSegmentBuffer.getRegister();
  198   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  201   return ArgInfo.DispatchPtr.getRegister();
  205   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  208   return ArgInfo.QueuePtr.getRegister();
  212   ArgInfo.KernargSegmentPtr
  216   return ArgInfo.KernargSegmentPtr.getRegister();
  220   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  223   return ArgInfo.DispatchID.getRegister();
  227   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  230   return ArgInfo.FlatScratchInit.getRegister();
  234   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  237   return ArgInfo.ImplicitBufferPtr.getRegister();
lib/Target/AMDGPU/SIMachineFunctionInfo.h
  543     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
  545     return ArgInfo.WorkGroupIDX.getRegister();
  549     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
  551     return ArgInfo.WorkGroupIDY.getRegister();
  555     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
  557     return ArgInfo.WorkGroupIDZ.getRegister();
  561     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
  563     return ArgInfo.WorkGroupInfo.getRegister();
  568     ArgInfo.WorkItemIDX = Arg;
  572     ArgInfo.WorkItemIDY = Arg;
  576     ArgInfo.WorkItemIDZ = Arg;
  580     ArgInfo.PrivateSegmentWaveByteOffset
  583     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
  587     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
  655     return ArgInfo;
  659     return ArgInfo;
  664     return ArgInfo.getPreloadedValue(Value);
  668     auto Arg = ArgInfo.getPreloadedValue(Value).first;
  693     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
  739     return ArgInfo.QueuePtr.getRegister();
  743     return ArgInfo.ImplicitBufferPtr.getRegister();
  859       return ArgInfo.WorkGroupIDX.getRegister();
  862       return ArgInfo.WorkGroupIDY.getRegister();
  865       return ArgInfo.WorkGroupIDZ.getRegister();