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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/AMDGPU/SILowerControlFlow.cpp 187 TII->isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term;
212 bool SimpleIf = isSimpleIf(MI, MRI, TII);
219 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
226 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
235 BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
244 BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
249 MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
295 BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
303 BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
312 BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
321 BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)
326 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
375 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Dst)
378 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
382 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
400 BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)
405 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
426 MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
496 TII = ST.getInstrInfo();
497 TRI = &TII->getRegisterInfo();