reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
758 const InstClassEnum InstClass = getInstClass(Opc, *TII); 763 const unsigned InstSubclass = getInstSubclass(Opc, *TII); 779 if ((getInstClass(MBBI->getOpcode(), *TII) != InstClass) || 780 (getInstSubclass(MBBI->getOpcode(), *TII) != InstSubclass)) { 829 CI.setPaired(MBBI, *TII); 835 ? dmasksCanBeCombined(CI, *TII) 877 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); 879 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); 880 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdst); 899 const MCInstrDesc &Read2Desc = TII->get(Opc); 912 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) 918 TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg) 935 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); 977 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); 979 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); 981 TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::data0); 997 const MCInstrDesc &Write2Desc = TII->get(Opc); 1005 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) 1011 TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg) 1050 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg); 1073 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); 1074 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1075 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata); 1111 BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg) 1112 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) 1123 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); 1124 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); 1125 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::sdst); 1154 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg); 1156 const unsigned Regs = getRegs(Opcode, *TII); 1159 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1170 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) 1171 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) 1185 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); 1186 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1187 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata); 1310 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1311 const auto *Src1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata); 1313 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) 1319 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode)) 1322 const unsigned Regs = getRegs(Opcode, *TII); 1325 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1337 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) 1338 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) 1357 if (TII->isInlineConstant(V)) 1363 TII->get(AMDGPU::S_MOV_B32), Reg) 1397 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_I32_e64), DestSub0) 1406 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) 1417 BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::REG_SEQUENCE), FullDestReg) 1432 TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase); 1433 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); 1484 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); 1485 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); 1496 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); 1497 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); 1527 if (MI.mayLoad() && TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL) 1535 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { 1541 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); 1600 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) 1604 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); 1694 const InstClassEnum InstClass = getInstClass(MI.getOpcode(), *TII); 1703 CI.setMI(MI, *TII, *STM); 1772 CI.setMI(NewMI, *TII, *STM); 1780 CI.setMI(NewMI, *TII, *STM); 1788 CI.setMI(NewMI, *TII, *STM); 1797 CI.setMI(NewMI, *TII, *STM); 1806 CI.setMI(NewMI, *TII, *STM); 1815 CI.setMI(NewMI, *TII, *STM); 1837 TII = STM->getInstrInfo(); 1838 TRI = &TII->getRegisterInfo();