reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
903 Register DestReg = MRI->createVirtualRegister(SuperRC); 911 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 915 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1004 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 1008 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1045 Register DestReg = MRI->createVirtualRegister(SuperRC); 1099 Register DestReg = MRI->createVirtualRegister(SuperRC); 1151 Register DestReg = MRI->createVirtualRegister(SuperRC); 1308 Register SrcReg = MRI->createVirtualRegister(SuperRC); 1360 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 1377 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 || 1381 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || 1391 Register CarryReg = MRI->createVirtualRegister(CarryRC); 1392 Register DeadCarryReg = MRI->createVirtualRegister(CarryRC); 1394 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1395 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1415 Register FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass); 1444 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg()); 1467 MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg()); 1477 MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(BaseLo.getReg()); 1478 MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(BaseHi.getReg()); 1705 if (!CI.hasMergeableAddress(*MRI)) 1840 MRI = &MF.getRegInfo(); 1843 assert(MRI->isSSA() && "Must be run on SSA");