reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
426 I = MI; 453 DMask0 = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); 456 Offset0 = I->getOperand(OffsetIdx).getImm(); 459 Width0 = getOpcodeWidth(*I, TII); 464 GLC0 = TII.getNamedOperand(*I, AMDGPU::OpName::glc)->getImm(); 466 SLC0 = TII.getNamedOperand(*I, AMDGPU::OpName::slc)->getImm(); 468 DLC0 = TII.getNamedOperand(*I, AMDGPU::OpName::dlc)->getImm(); 473 const unsigned Regs = getRegs(I->getOpcode(), TII); 500 AddrIdx[i] = AMDGPU::getNamedOperandIdx(I->getOpcode(), AddrOpName[i]); 501 AddrReg[i] = &I->getOperand(AddrIdx[i]); 516 AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::offset); 642 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); 643 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); 654 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); 658 CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm()) 753 MachineBasicBlock *MBB = CI.I->getParent(); 755 MachineBasicBlock::iterator MBBI = CI.I; 757 const unsigned Opc = CI.I->getOpcode(); 767 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::swz); 768 if (Swizzled != -1 && CI.I->getOperand(Swizzled).getImm()) 775 addDefsUsesToList(*CI.I, RegDefsToMove, PhysRegUsesToMove); 794 (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) || 850 if (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) || 873 MachineBasicBlock *MBB = CI.I->getParent(); 877 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); 879 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); 905 DebugLoc DL = CI.I->getDebugLoc(); 931 .cloneMergedMemRefs({&*CI.I, &*CI.Paired}); 947 CI.I->eraseFromParent(); 972 MachineBasicBlock *MBB = CI.I->getParent(); 977 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); 979 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); 998 DebugLoc DL = CI.I->getDebugLoc(); 1026 .cloneMergedMemRefs({&*CI.I, &*CI.Paired}); 1030 CI.I->eraseFromParent(); 1039 MachineBasicBlock *MBB = CI.I->getParent(); 1040 DebugLoc DL = CI.I->getDebugLoc(); 1048 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); 1051 for (unsigned I = 1, E = (*CI.I).getNumOperands(); I != E; ++I) { 1055 MIB.add((*CI.I).getOperand(I)); 1061 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand()); 1063 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); 1074 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1086 CI.I->eraseFromParent(); 1093 MachineBasicBlock *MBB = CI.I->getParent(); 1094 DebugLoc DL = CI.I->getDebugLoc(); 1105 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand()); 1107 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); 1112 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) 1124 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); 1136 CI.I->eraseFromParent(); 1143 MachineBasicBlock *MBB = CI.I->getParent(); 1144 DebugLoc DL = CI.I->getDebugLoc(); 1159 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1164 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand()); 1166 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); 1170 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) 1171 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) 1186 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1198 CI.I->eraseFromParent(); 1210 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), 1225 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); 1297 MachineBasicBlock *MBB = CI.I->getParent(); 1298 DebugLoc DL = CI.I->getDebugLoc(); 1310 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); 1325 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1331 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand()); 1333 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); 1337 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) 1338 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) 1349 CI.I->eraseFromParent(); 1667 if (AddrList.front().hasSameBaseAddress(*CI.I) && 1749 if (&*CI->I == &MI) {