reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
435 EltSize = 440 EltSize = 445 EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4); 448 EltSize = 4; 682 if ((CI.Offset0 % CI.EltSize != 0) || (CI.Offset1 % CI.EltSize != 0)) 682 if ((CI.Offset0 % CI.EltSize != 0) || (CI.Offset1 % CI.EltSize != 0)) 685 unsigned EltOffset0 = CI.Offset0 / CI.EltSize; 686 unsigned EltOffset1 = CI.Offset1 / CI.EltSize; 720 CI.Offset0 = (EltOffset0 - CI.BaseOff / CI.EltSize) / 64; 721 CI.Offset1 = (EltOffset1 - CI.BaseOff / CI.EltSize) / 64; 727 CI.Offset0 = EltOffset0 - CI.BaseOff / CI.EltSize; 728 CI.Offset1 = EltOffset1 - CI.BaseOff / CI.EltSize; 885 CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize); 885 CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize); 887 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; 888 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; 902 (CI.EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass; 986 CI.UseST64 ? write2ST64Opcode(CI.EltSize) : write2Opcode(CI.EltSize); 986 CI.UseST64 ? write2ST64Opcode(CI.EltSize) : write2Opcode(CI.EltSize);