reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1451 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; 1452 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; 1463 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; 1464 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; 1533 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 1540 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64)); 2440 (ST.getConstantBusLimit(Opc) <= 1 && 2443 (ST.getConstantBusLimit(Opc) <= 1 && 2655 (ST.getConstantBusLimit(Opc) > 1 || 2817 ST.hasInv2PiInlineImm()); 2820 ST.hasInv2PiInlineImm()); 2822 return ST.has16BitInsts() && 2824 ST.hasInv2PiInlineImm()); 2851 return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm()); 2858 ST.hasInv2PiInlineImm()); 2871 return ST.has16BitInsts() && 2872 AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm()); 2884 return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm()); 3302 if (!ST.hasSDWA()) { 3316 if (!ST.hasSDWAScalar()) { 3331 if (!ST.hasSDWAOmod()) { 3343 if (!ST.hasSDWASdst() && DstIdx != -1) { 3350 } else if (!ST.hasSDWAOutModsVOPC()) { 3404 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem()) 3506 if (SGPRCount > ST.getConstantBusLimit(Opcode)) { 3705 ST.getGeneration() >= AMDGPUSubtarget::GFX10) { 3711 ST.getGeneration() >= AMDGPUSubtarget::GFX10) { 3717 ST.getGeneration() < AMDGPUSubtarget::GFX10) { 3744 return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_I32_e32; 3748 return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; 3763 return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END; 4026 if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && 4155 int ConstantBusLimit = ST.getConstantBusLimit(Opc); 4156 int LiteralLimit = ST.hasVOP3Literal() ? 1 : 0; 4734 } else if (!VAddr && ST.hasAddr64()) { 4872 if (ST.hasDLInsts()) 4905 if (ST.hasOnlyRevVALUShifts()) { 4911 if (ST.hasOnlyRevVALUShifts()) { 4917 if (ST.hasOnlyRevVALUShifts()) { 4923 if (ST.hasOnlyRevVALUShifts()) { 4929 if (ST.hasOnlyRevVALUShifts()) { 4935 if (ST.hasOnlyRevVALUShifts()) { 4949 if (ST.isWave32()) 5103 if (ST.hasAddNoCarry()) { 5148 unsigned SubOp = ST.hasAddNoCarry() ? 5174 if (ST.hasDLInsts()) { 5862 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) { 5869 if (ST.isAmdHsaOS()) { 5871 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS) 5876 if (ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) 5889 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 5890 uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize()) - 1; 5895 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; 5900 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS && 5901 ST.getGeneration() <= AMDGPUSubtarget::GFX9) 6193 if (ST.hasAddNoCarry()) 6209 if (ST.hasAddNoCarry()) 6271 if (!ST.hasFlatInstOffsets()) 6274 if (ST.hasFlatSegmentOffsetBug() && AddrSpace == AMDGPUAS::FLAT_ADDRESS) 6277 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) 6286 if (!ST.hasFlatInstOffsets()) 6289 if (ST.hasFlatSegmentOffsetBug() && AddrSpace == AMDGPUAS::FLAT_ADDRESS) 6292 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) { 6331 SIEncodingFamily Gen = subtargetEncodingFamily(ST); 6334 ST.getGeneration() == AMDGPUSubtarget::GFX9) 6340 if (ST.hasUnpackedD16VMem() && (get(Opcode).TSFlags & SIInstrFlags::D16Buf)) 6344 switch (ST.getGeneration()) { 6550 get(ST.isWave32() ? AMDGPU::S_MOV_B32_term 6560 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }