reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/SIInstrInfo.h

  798   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,

References

lib/Target/AMDGPU/SIAddIMGInit.cpp

  127               RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
  133               MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
  151                   MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  664         if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) ||
  794         TII->getOpRegClass(*UseMI, UseMI->getOperandNo(&Use));

lib/Target/AMDGPU/SIInsertWaitcnts.cpp

  494   const TargetRegisterClass *RC = TII->getOpRegClass(MIA, OpNo);

lib/Target/AMDGPU/SIInstrInfo.cpp

  299         EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
  303         EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
 3415         const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
 3669         const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
 4557     if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
 4560         if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) {
 4563           VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
 4567           VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
 4597     const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
 5640     if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) {
 5736   const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
 5749     const TargetRegisterClass *SrcRC = getOpRegClass(Inst, 1);

lib/Target/AMDGPU/SIInstrInfo.h

  828     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;