reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
4520 legalizeOperandsVOP2(MRI, MI); 4526 legalizeOperandsVOP3(MRI, MI); 4532 legalizeOperandsSMRD(MRI, MI); 4546 MRI.getRegClass(MI.getOperand(i).getReg()); 4588 legalizeGenericOperand(*InsertBB, Insert, RC, Op, MRI, MI.getDebugLoc()); 4607 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); 4612 legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc()); 4625 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 4626 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); 4630 legalizeGenericOperand(*MBB, MI, DstRC, Op, MRI, MI.getDebugLoc()); 4638 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg()))) 4639 Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI)); 4652 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { 4653 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); 4658 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) { 4659 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI); 4672 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), 4698 Register NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 4699 Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); 4700 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); 4703 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC); 4704 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC); 4744 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);