reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
4014 unsigned Opc = MI.getOpcode(); 4018 MachineOperand &Src0 = MI.getOperand(Src0Idx); 4021 MachineOperand &Src1 = MI.getOperand(Src1Idx); 4025 bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister; 4029 legalizeOpWithMove(MI, Src0Idx); 4035 const DebugLoc &DL = MI.getDebugLoc(); 4038 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4038 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4044 const DebugLoc &DL = MI.getDebugLoc(); 4045 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4045 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4054 legalizeOpWithMove(MI, Src0Idx); 4057 legalizeOpWithMove(MI, Src1Idx); 4070 const DebugLoc &DL = MI.getDebugLoc(); 4071 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4071 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) 4081 if (HasImplicitSGPR || !MI.isCommutable()) { 4082 legalizeOpWithMove(MI, Src1Idx); 4093 legalizeOpWithMove(MI, Src1Idx); 4097 int CommutedOpc = commuteOpcode(MI); 4099 legalizeOpWithMove(MI, Src1Idx); 4103 MI.setDesc(get(CommutedOpc)); 4119 fixImplicitOperands(MI);