reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/SIInstrInfo.cpp
 4823     MachineBasicBlock *MBB = Inst.getParent();
 4826     unsigned Opcode = Inst.getOpcode();
 4827     unsigned NewOpcode = getVALUOp(Inst);
 4835       splitScalar64BitAddSub(Worklist, Inst, MDT);
 4836       Inst.eraseFromParent();
 4841       if (moveScalarAddSub(Worklist, Inst, MDT))
 4847       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
 4848       Inst.eraseFromParent();
 4852       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
 4853       Inst.eraseFromParent();
 4857       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32, MDT);
 4858       Inst.eraseFromParent();
 4862       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NAND_B32, MDT);
 4863       Inst.eraseFromParent();
 4867       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NOR_B32, MDT);
 4868       Inst.eraseFromParent();
 4873         splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32, MDT);
 4875         splitScalar64BitXnor(Worklist, Inst, MDT);
 4876       Inst.eraseFromParent();
 4880       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
 4881       Inst.eraseFromParent();
 4885       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ORN2_B32, MDT);
 4886       Inst.eraseFromParent();
 4890       splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
 4891       Inst.eraseFromParent();
 4895       splitScalar64BitBCNT(Worklist, Inst);
 4896       Inst.eraseFromParent();
 4900       splitScalar64BitBFE(Worklist, Inst);
 4901       Inst.eraseFromParent();
 4907         swapOperands(Inst);
 4913         swapOperands(Inst);
 4919         swapOperands(Inst);
 4925         swapOperands(Inst);
 4931         swapOperands(Inst);
 4937         swapOperands(Inst);
 4942       lowerScalarAbs(Worklist, Inst);
 4943       Inst.eraseFromParent();
 4950         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
 4950         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
 4955         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
 4955         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
 4968       movePackToVALU(Worklist, MRI, Inst);
 4969       Inst.eraseFromParent();
 4973       lowerScalarXnor(Worklist, Inst);
 4974       Inst.eraseFromParent();
 4978       splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
 4979       Inst.eraseFromParent();
 4983       splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
 4984       Inst.eraseFromParent();
 4988       splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
 4989       Inst.eraseFromParent();
 4993       splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
 4994       Inst.eraseFromParent();
 5001       legalizeOperands(Inst, MDT);
 5007     Inst.setDesc(NewDesc);
 5012     for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) {
 5013       MachineOperand &Op = Inst.getOperand(i);
 5017           addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
 5018         Inst.RemoveOperand(i);
 5026       Inst.addOperand(MachineOperand::CreateImm(0));
 5027       Inst.addOperand(MachineOperand::CreateImm(Size));
 5032       Inst.addOperand(MachineOperand::CreateImm(0));
 5035     Inst.addImplicitDefUseOperands(*Inst.getParent()->getParent());
 5035     Inst.addImplicitDefUseOperands(*Inst.getParent()->getParent());
 5036     fixImplicitOperands(Inst);
 5039       const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
 5048       Inst.RemoveOperand(2);                     // Remove old immediate.
 5049       Inst.addOperand(MachineOperand::CreateImm(Offset));
 5050       Inst.addOperand(MachineOperand::CreateImm(BitWidth));
 5053     bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
 5053     bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
 5056       Register DstReg = Inst.getOperand(0).getReg();
 5061       const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
 5065       if (Inst.isCopy() &&
 5066           Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
 5067           NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
 5075         MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
 5076         MRI.clearKillFlags(Inst.getOperand(1).getReg());
 5077         Inst.getOperand(0).setReg(DstReg);
 5082         for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
 5083           Inst.RemoveOperand(I);
 5084         Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
 5093     legalizeOperands(Inst, MDT);