reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  841   if (MI.isDebugInstr())
  848   if (MI.getOpcode() == AMDGPU::BUFFER_WBINVL1 ||
  849       MI.getOpcode() == AMDGPU::BUFFER_WBINVL1_SC ||
  850       MI.getOpcode() == AMDGPU::BUFFER_WBINVL1_VOL ||
  851       MI.getOpcode() == AMDGPU::BUFFER_GL0_INV ||
  852       MI.getOpcode() == AMDGPU::BUFFER_GL1_INV) {
  859   if (MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG ||
  860       MI.getOpcode() == AMDGPU::S_SETPC_B64_return ||
  861       (MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) {
  861       (MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) {
  861       (MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) {
  865   else if ((MI.getOpcode() == AMDGPU::S_SENDMSG ||
  866             MI.getOpcode() == AMDGPU::S_SENDMSGHALT) &&
  867            ((MI.getOperand(0).getImm() & AMDGPU::SendMsg::ID_MASK_) ==
  930     if (MI.modifiesRegister(AMDGPU::EXEC, TRI)) {
  941     if (MI.isCall() && callWaitsOnFunctionEntry(MI)) {
  941     if (MI.isCall() && callWaitsOnFunctionEntry(MI)) {
  948           AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
  950           &MI, TII, MRI, TRI, CallAddrOpIdx, false);
  958             AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
  961             &MI, TII, MRI, TRI, RtnAddrOpIdx, false);
  977       for (const MachineMemOperand *Memop : MI.memoperands()) {
  987       for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
  988         const MachineOperand &Op = MI.getOperand(I);
  991             ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, false);
 1010       if (MI.mayStore()) {
 1012         for (const MachineMemOperand *Memop : MI.memoperands()) {
 1023       for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
 1024         MachineOperand &Def = MI.getOperand(I);
 1027             ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, true);
 1046   if (MI.getOpcode() == AMDGPU::S_BARRIER &&
 1054   if (readsVCCZ(MI) && ST->hasReadVCCZBug()) {
 1067            &*II != &MI; II = NextI, ++NextI) {
 1108          &*II != &MI; II = NextI, NextI++) {
 1142                         << "Old Instr: " << MI << '\n'
 1152     auto SWaitInst = BuildMI(*MI.getParent(), MI.getIterator(),
 1152     auto SWaitInst = BuildMI(*MI.getParent(), MI.getIterator(),
 1153                              MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
 1159                       << "Old Instr: " << MI << '\n'
 1167         BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
 1167         BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
 1167         BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
 1175                       << "Old Instr: " << MI << '\n'