reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
145 if (Subtarget->has16BitInsts()) { 156 if (Subtarget->hasMAIInsts()) { 161 computeRegisterProperties(Subtarget->getRegisterInfo()); 347 if (Subtarget->hasFlatAddressSpace()) { 360 if (Subtarget->has16BitInsts()) { 367 if (!Subtarget->hasFP32Denormals()) 370 if (!Subtarget->hasBFI()) { 376 if (!Subtarget->hasBCNT(32)) 379 if (!Subtarget->hasBCNT(64)) 382 if (Subtarget->hasFFBH()) 385 if (Subtarget->hasFFBL()) 396 if (Subtarget->hasBFE()) 414 if (Subtarget->haveRoundOpsF64()) { 432 if (Subtarget->has16BitInsts()) { 506 if (!Subtarget->hasFP16Denormals() && STI.hasMadF16()) 575 if (!Subtarget->hasVOP3PInsts()) { 597 if (Subtarget->hasVOP3PInsts()) { 655 if (Subtarget->has16BitInsts()) { 753 return Subtarget; 766 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || 767 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && 768 DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() && 793 if (Size == 16 && Subtarget->has16BitInsts()) 818 if (Size == 16 && Subtarget->has16BitInsts()) 851 if (Size == 16 && Subtarget->has16BitInsts()) { 1066 if (!Subtarget->hasFlatInstOffsets()) { 1079 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) 1087 if (Subtarget->hasFlatGlobalInsts()) 1090 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) { 1090 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) { 1167 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) { 1171 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) { 1176 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 1256 if (!Subtarget->hasUnalignedScratchAccess() && 1266 if (Subtarget->hasUnalignedBufferAccess()) { 1372 if (Subtarget->has16BitInsts() && VT == MVT::i16) { 1991 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); 2028 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) { 2070 if (Subtarget->isAmdPalOS()) { 2144 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS && 2342 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 2444 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 2834 : commonAlignment(Subtarget->getStackAlignment(), Offset); 2854 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset); 2946 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo()); 3000 if (!Subtarget->hasFlatScrRegister() && 3001 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) { 3925 if (Subtarget->hasFP32Denormals()) 3926 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts(); 3926 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts(); 3929 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts(); 3929 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts(); 3934 return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals(); 3934 return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals(); 4120 bool Unpacked = Subtarget->hasUnpackedD16VMem(); 4606 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa || 4607 !Subtarget->isTrapHandlerEnabled()) 4633 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa || 4634 !Subtarget->isTrapHandlerEnabled()) { 4654 if (Subtarget->hasApertureRegs()) { 4982 assert(!Subtarget->hasVOP3PInsts() && "this should be legal"); 5329 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10; 5374 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16) 5387 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16) 5398 if (IsD16 && !Subtarget->hasUnpackedD16VMem()) 5608 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 5630 Subtarget->hasUnpackedD16VMem(), IsD16, 5724 if (!Subtarget->isAmdHsaOrMesa(MF.getFunction())) { 5754 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 5759 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) 5763 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) 5777 if (Subtarget->isAmdHsaOS()) 5783 if (Subtarget->isAmdHsaOS()) 5789 if (Subtarget->isAmdHsaOS()) 5795 if (Subtarget->isAmdHsaOS()) 5801 if (Subtarget->isAmdHsaOS()) 5807 if (Subtarget->isAmdHsaOS()) 5813 if (Subtarget->isAmdHsaOS()) 5819 if (Subtarget->isAmdHsaOS()) 5825 if (Subtarget->isAmdHsaOS()) 5861 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10; 5942 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) 6135 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) { 6182 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) 6717 if (!Subtarget->hasDwordx3LoadStores() && 6751 if (Subtarget->hasUnpackedD16VMem()) { 7168 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, Align)) { 7181 Subtarget, Align)) { 7382 if (Subtarget->hasLDSMisalignedBug() && 7416 if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() && 7437 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores()) 7446 switch (Subtarget->getMaxPrivateElementSize()) { 7458 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores()) 7466 if (Subtarget->useDS128() && Load->getAlignment() >= 16 && 7478 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS && 7525 if (!Unsafe && VT == MVT::f32 && Subtarget->hasFP32Denormals()) 7704 if (!Subtarget->hasFP32Denormals()) { 7708 if (Subtarget->hasDenormModeInst()) { 7710 getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, SL, Subtarget); 7748 if (!Subtarget->hasFP32Denormals()) { 7751 if (Subtarget->hasDenormModeInst()) { 7753 getSPDenormModeValue(FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, SL, Subtarget); 7813 if (!Subtarget->hasUsableDivScaleConditionOutput()) { 7881 if (Subtarget->hasLDSMisalignedBug() && 7901 if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores()) 7905 switch (Subtarget->getMaxPrivateElementSize()) { 7921 if (Subtarget->useDS128() && Store->getAlignment() >= 16 && 7933 if (!Subtarget->hasUsableDSOffset() && 7955 if (Subtarget->hasTrigReducedRange()) { 8618 if (!Subtarget->has16BitInsts() || 8791 if (Subtarget->supportsMinMaxDenormModes() || 9032 if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->hasMed3_16())) { 9092 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasMed3_16())) { 9130 ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) { 9174 (VT == MVT::f16 && Subtarget->has16BitInsts()) || 9175 (VT == MVT::v2f16 && Subtarget->hasVOP3PInsts())) && 9413 if (((VT == MVT::f32 && !Subtarget->hasFP32Denormals()) || 9414 (VT == MVT::f16 && !Subtarget->hasFP16Denormals() && 9489 && Subtarget->hasMad64_32() && 9700 if (!Subtarget->hasDot2Insts() || VT != MVT::f32) 9833 if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() && 10401 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 10606 if (!Subtarget->hasMAIInsts()) 10678 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 10883 return Subtarget->hasFP32Denormals(); 10885 return Subtarget->hasFP64Denormals(); 10887 return Subtarget->hasFP16Denormals(); 10926 return (AS == AMDGPUAS::LOCAL_ADDRESS && Subtarget->hasLDSFPAtomics()) ? 10939 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 10941 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass 11017 const SIRegisterInfo *SIRI = Subtarget->getRegisterInfo(); 11020 MF.getDataLayout(), Subtarget->getRegisterInfo(), CS);