reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/SIISelLowering.cpp
 4014   switch (Op.getOpcode()) {
 4015   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
 4016   case ISD::BRCOND: return LowerBRCOND(Op, DAG);
 4017   case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
 4019     SDValue Result = LowerLOAD(Op, DAG);
 4028     return LowerTrig(Op, DAG);
 4029   case ISD::SELECT: return LowerSELECT(Op, DAG);
 4030   case ISD::FDIV: return LowerFDIV(Op, DAG);
 4031   case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
 4032   case ISD::STORE: return LowerSTORE(Op, DAG);
 4036     return LowerGlobalAddress(MFI, Op, DAG);
 4038   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
 4039   case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
 4040   case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
 4041   case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
 4043     return lowerINSERT_SUBVECTOR(Op, DAG);
 4045     return lowerINSERT_VECTOR_ELT(Op, DAG);
 4047     return lowerEXTRACT_VECTOR_ELT(Op, DAG);
 4049     return lowerVECTOR_SHUFFLE(Op, DAG);
 4051     return lowerBUILD_VECTOR(Op, DAG);
 4053     return lowerFP_ROUND(Op, DAG);
 4055     return lowerTRAP(Op, DAG);
 4057     return lowerDEBUGTRAP(Op, DAG);
 4061     return splitUnaryVectorOp(Op, DAG);
 4064     return lowerFMINNUM_FMAXNUM(Op, DAG);
 4066     return splitTernaryVectorOp(Op, DAG);
 4081     return splitBinaryVectorOp(Op, DAG);