reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
3587 if (TII->isMIMG(MI)) { 3588 if (MI.memoperands_empty() && MI.mayLoadOrStore()) { 3588 if (MI.memoperands_empty() && MI.mayLoadOrStore()) { 3597 switch (MI.getOpcode()) { 3604 const DebugLoc &DL = MI.getDebugLoc(); 3606 MachineOperand &Dest = MI.getOperand(0); 3607 MachineOperand &Src0 = MI.getOperand(1); 3608 MachineOperand &Src1 = MI.getOperand(2); 3613 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI, 3616 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI, 3620 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI, 3623 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI, 3627 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO); 3631 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) 3634 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) 3637 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg()) 3642 MI.eraseFromParent(); 3646 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), 3646 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), 3648 .add(MI.getOperand(0)); 3649 MI.eraseFromParent(); 3654 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), 3656 .addImm(MI.getOperand(0).getImm()); 3657 MI.eraseFromParent(); 3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), 3664 .addImm(MI.getOperand(0).getImm()); 3665 MI.eraseFromParent(); 3678 Register InputReg = MI.getOperand(0).getReg(); 3683 for (auto I = BB->begin(); I != &MI; I++) { 3706 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000); 3719 MI.eraseFromParent(); 3726 DebugLoc DL = MI.getDebugLoc(); 3727 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32)) 3728 .add(MI.getOperand(0)) 3730 MI.eraseFromParent(); 3738 return emitIndirectSrc(MI, *BB, *getSubtarget()); 3744 return emitIndirectDst(MI, *BB, *getSubtarget()); 3747 return splitKillBlock(MI, BB); 3753 Register Dst = MI.getOperand(0).getReg(); 3754 Register Src0 = MI.getOperand(1).getReg(); 3755 Register Src1 = MI.getOperand(2).getReg(); 3756 const DebugLoc &DL = MI.getDebugLoc(); 3757 Register SrcCond = MI.getOperand(3).getReg(); 3764 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy) 3766 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) 3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) 3779 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst) 3784 MI.eraseFromParent(); 3789 const DebugLoc &DL = MI.getDebugLoc(); 3790 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1)) 3791 .add(MI.getOperand(0)); 3793 MI.eraseFromParent(); 3799 MachineInstrBuilder MIB(*MF, &MI); 3811 const DebugLoc &DL = MI.getDebugLoc(); 3816 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg); 3818 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) 3819 MIB.add(MI.getOperand(I)); 3821 MIB.cloneMemRefs(MI); 3822 MI.eraseFromParent(); 3829 const DebugLoc &DL = MI.getDebugLoc(); 3830 unsigned Opc = MI.getOpcode(); 3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg()); 3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg()); 3844 I.add(MI.getOperand(1)) 3845 .add(MI.getOperand(2)); 3851 MI.eraseFromParent(); 3862 bundleInstWithWaitcnt(MI); 3866 return emitGWSMemViolTestLoop(MI, BB); 3868 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);